Bogdan Majkusiak

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO2 dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance

Influence of carrier energy quantization on threshold voltage of metal‐oxide‐semiconductor transistor

A new method for calculating free carrier energy quantization in the depletion region is proposed and applied to investigate the influence of this phenomenon on the metal‐oxide‐semiconductor transistor threshold voltage. This influence is significant when the semiconductor surface region is highly doped. Other phenomena essential for high doping levels such as the energy degeneration, the incomplete ionization of dopants, and the band‐gap narrowing are taken into account.

Experimental and theoretical study of the current-voltage characteristics of the MISIM tunnel transistor

Current-voltage (I-V) characteristics of the metal-insulator-semiconductor-insulator-metal (MISIM) tunnel transistor in the common base and common emitter configurations are studied experimentally and theoretically. The Al-SiO/sub 2/-Si(n)-SiO/sub 2/-Al transistors with oxide layers of about 2.5 nm thickness have been manufactured. The devices exhibit current gain above 30 in the common base configuration and switching in the common emitter configuration. A theoretical static model of the MISIM tunnel transistor has been developed and applied to analyze the measured I-V characteristics for both operation configurations. Excellent fit of the model to the experimental data has been achieved. Influence of oxide thickness and interface trap density on the switching voltage has been investigated theoretically.

The remote roughness mobility resulting from the ultrathin SiO2 thickness nonuniformity in the DG SOI and bulk MOS transistors

Abstract The influence of the SiO 2 thickness nonuniformity on the electron mobility in the n-channel Double Gate (DG) SOI and bulk MOS transistors is investigated based on self-consistent solution to Poisson and Schrodinger equations and within the relaxation time approximation. The mobility degradation induced by the SiO2 thickness nonuniformity is found to be of significant importance while scaling down the dielectric layer thickness and the semiconductor layer thickness in case of the SOI transistor.

Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide

The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode.

Small-signal admittance model as a characterization tool of the MOS tunnel diode

The tunnel leakage through the insulator layer of metal–insulator–semiconductor tunnel diodes and its small-signal admittance is investigated by means of a theoretical model of the metal–oxide–semiconductor tunnel diode based on a steady-state algorithm and the minority carrier relaxation time. The conclusions are reviewed using an experimental Al-SiO2-Si structure with an ultrathin oxide layer.

Theoretical Study of Electron Mobility in Double-Gate Field Effect Transistors with Multilayer (strained-)Si/SiGe Channel

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-oninsulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

Investigation of double barrier MOS tunnel diodes with PECVD silicon quantum well

Abstract Double barrier metal–oxide–semiconductor tunnel diodes with ultrathin PECVD Si and thermal SiO 2 layers were fabricated. The measured capacitance–voltage and current–voltage characteristics were interpreted and physical parameters of the structures were extracted by means of a theoretical model.

Electron energy quantization effects in the very thin film GAA SOI transistor

Abstract Analysis of the energy quantization effects on the semiconductor region of the Gate-All-Around SOI transistor, based on the self-consistent solution to the Schrodinger and Poisson equations is presented in dependence on the gate voltage and semiconductor film thickness. For thicker semiconductor films the energy quantization manifests mainly at high surface potentials due to the confinement of electron wave functions in the potential wells at the surfaces. When the semiconductor film is very thin the quantization due to the confinement of electrons in the semiconductor film dominates and the maximum of electron concentration is located in the middle of it, supporting the concept of volume inversion. Upon increasing the gate voltage the concentration peak splits into two ones.

Comparison of advanced transport models for nanoscale nMOSFETs

In this paper we mutually compare advanced modeling approaches for the determination of the drain current in nanoscale MOSFETs. Transport models range from Drift-Diffusion to direct solution of the Boltzmann Transport equation with the Monte-Carlo methods. Template devices representative of 22nm Double-Gate and 32nm FDSOI transistors were used as a common benchmark to highlight the differences between the quantitative predictions of different approaches. Our results set a benchmark to assess modeling tools for nanometric MOSFETs.