Jakub Jasiński

Small-signal admittance model as a characterization tool of the MOS tunnel diode

The tunnel leakage through the insulator layer of metal–insulator–semiconductor tunnel diodes and its small-signal admittance is investigated by means of a theoretical model of the metal–oxide–semiconductor tunnel diode based on a steady-state algorithm and the minority carrier relaxation time. The conclusions are reviewed using an experimental Al-SiO2-Si structure with an ultrathin oxide layer.

Effect of inner interface traps on high-k gate stack admittance characteristics

Admittance parameters analysis can give useful information on traps located at the inner interface in high-k gate stacks. The presented study reveals that conductance characteristics are more valuable for characterization procedure then capacitance ones. It particularly considers structures in which tunnel communication via traps cannot be neglected.

Studies of the quality of GdSiO―Si interface

Abstract In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods ( C – V , I – V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C – V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.

Modeling high-frequency capacitance in SOI MOS capacitors

This paper presents a model of high frequency capacitance of a SOI MOSCAP. The capacitance in strong inversion is described with minority carrier redistribution in the inversion layer taken into account. The efficiency of the computational process is significantly improved. Moreover, it is suitable for the simulation of thin-film SOI structures. It may also be applied to the characterization of non-standard SOI MOSCAPS e.g. with nanocrystalline body.

Simulation of electrical characteristics of GaN vertical Schottky diodes

Reverse current of GaN vertical Schottky diodes is simulated using Silvaco ATLAS to optimize the geometry for the best performance. Several physical quantities and phenomena, such as carrier mobility and tunneling mechanism are studied to select the most realistic models. Breakdown voltage is qualitatively estimated based on the maximum electric field in the structure.

Effect of interface traps parameters on admittance characteristics of the MIS (metal-insulator-semiconductor) tunnel structures

Interface traps density (Nit) and gate insulator thickness (tox) impact on MIS tunnel structure electrical characteristics is discussed in respect to bias voltage range corresponding to inversion in the semiconductor substrate region. Effect of Nit and tox on equilibrium and non-equilibrium operation regime of the device is presented. Different models of the small-signal response of interface traps are proposed and discussed in respect to several phenomena related to the traps charging and discharging processes. Presented analysis was performed for the MIS structures with the gate dielectric made of silicon dioxide (SiO2) and hafnium oxide (HfOx). The obtained results proved that the surface density of interface traps (Nit) and the insulator thickness (tox) have correlated impact on the transition between equilibrium and non-equilibrium operation of the MIS tunnel structures.

Influence of series resistance determination on the extracted mobility in MOS transistors with Ge channel

The influence of the method of series resistance determination on the extracted channel mobility is investigated in MOS transistors with relaxed and strained Ge channel. The dependence of the extracted mobility on the channel length and the frequency of the signal used to measure capacitance-voltage characteristics are examined.

Electrical characterization of GaN-channel MOSFETs

The channel mobility and reliability of NMOSFETs with GaN channel are investigated by means of split CV and constant-voltage-stress techniques. The influence of stress polarity and duration on current in the off-state, threshold voltage and subthreshold slope is studied.