Bojan Jovanovic

Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions

In the last few years, spintronics has attracted the full attention of the scientific community for the synergy it provides to conventional complimentary metal-oxide-semiconductor (CMOS) devices (nonvolatility, infinite endurance, radiation immunity, increased density, and so on). Many hybrid (magnetic/CMOS) cells have been proposed which can store and process data in both electrical and magnetic ways. Such cells are mainly based on magnetic tunnel junctions (MTJs) and are suitable for use in magnetic random access memories (MRAMs) and reprogrammable computing (magnetic FPGAs, nonvolatile registers, processor cache memories, and so on). In this paper, we report the results of exhaustive energy-performance analysis of the set of hybrid cells recently published in the literature. We explore their limits in metrics of the required silicon area, robustness, read/write speed, and consumed energy. Two different mechanisms for writing non-volatile data stored in MTJs are applied to each hybrid cell: thermally assisted switching (TAS) and spin-transfer torque (STT). All the results were obtained through simulations in Cadence Spectre 7.2. For the CMOS part, we used 45 nm predictive transistor models whereas the MTJ part was simulated using the 120 nm × 120 nm TAS Spintec model and the 100 nm × 50 nm STT Spinlib model. The results presented here are a valuable resource for future designers of hybrid devices if they need to select an appropriate hybrid cell for a target application.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

Ater decades of continued scaling to the beat of Moores law, it now appears that conventional silicon based devices are approaching their physical limits. In todays deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

Power models are at the heart of high-level estimation methods used for industrial power evaluation of FPGA-based electronic designs. In this paper, probabilistic power estimation models of binary divider IP cores implemented in reconfigurable logic are presented. The models are ready for use at the algorithmic and RTL levels of the design flow and are simulation-independent, thus resulting in fast estimation times. The only parameters the model needs are the bit-widths of the operator inputs and their signal statistics: mean values, variances and autocorrelation coefficients. Based on these parameters and taking into account the particular logic structure of the binary divider cores, analytical probabilistic formulas are used to calculate the overall switching activity in the circuits-the main cause of dynamic power consumption. Estimates are compared with both real on-board measurements and estimates from the simulation-based tool XPower from Xilinx. Results show that the mean relative estimation errors are within 10% of on-board measurements or low-level estimates, and the average time to obtain power estimates using the proposed models is only 135 ms.

Power estimation of dividers implemented in FPGAs

We present a methodology for power estimation of non-fractional divider cores implemented in FPGAs. The methodology takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool.

Is children's motor learning of a postural reaching task enhanced by practice in a virtual environment?

To support the use of virtual environments (VEs) in pediatric rehabilitation, greater understanding of the extent and mechanisms by which practice in a VE might facilitate motor learning as compared to practice in a physical environment (PE) is required. One proposed mechanism is via enhanced user engagement and/or motivation, which may directly influence the quality of motor memory consolidation. The objectives of this study were to a) compare childrens motor learning of the same novel postural reaching task in a VE versus a PE; b) evaluate differences in engagement and motivation between the two practice environments; and c) explore the relationships between practice environment, engagement, motivation, and motor learning. Thirty-six typically developing children aged 7–13 years were randomized to acquire a novel postural reaching skill in either a 2D flat-screen VE or a PE. Skin conductance level (SCL) was measured on the non-task hand during practice. Following acquisition, children completed a language-modified User Engagement Scale (UES) and the Pediatric Motivation Inventory (PMOT). Participants returned 1–7 days later for retention (same environment) and transfer (opposite environment) tests. Children who practiced in the VE demonstrated greater retention, as evidenced by higher mean scores on the retention test (t[30] = −3.72, p = 0.001, partial eta squared 0.28). Children who practiced in the PE demonstrated greater transfer to the opposite environment as compared to those who practiced in the VE (t[30] = 2.05, p = 0.001, partial eta squared = 0.238). There were no significant differences in UES total or subscale scores between the 2 groups. PMOT total motivation scores differed significantly between groups, favoring the VE (t[30]= 2.49, p = 0.018, partial eta squared = 0.154). There were no significant differences in SCL peak count or peaks per minute between groups. There was no relationship between engagement, motivation, and retention or transfer performance. Findings suggest that retention but not transfer of a new motor skill may be facilitated by practice in a VE. This may be due to unique task demands in each environment. Children were more motivated to succeed in the VE and were engaged in the task in both environments, suggesting that both constructs should be measured in subsequent studies and that VE aesthetics alone may not be a key ‘active ingredient’ of childrens engagement. Subsequent research will more objectively quantify neurophysiological correlates of engagement and motivation, explore additional tasks, include populations with neurological impairments and compare 3D vs 2D VE displays.

Methods for power minimisation in modern VLSI circuits

The continued scaling of the CMOS technology has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. In this paper, we present some widely used techniques for static and dynamic power minimisation in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the designs architectural variations. Along with the overview of power minimisation techniques, as an example, the circuit of binary divider was introduced and implemented in various families FPGAs to demonstrate technological as well as Placement and Routing (PAR) influence on total power consumption.

Logic Circuits Design Based on MRAM: From Single to Multi-States Cells Storage

In recent years, conventional silicon-based high-speed computing circuits became increasingly power-hungry due to the leakage currents and accelerated data traffic. Furthermore, numerous short-channel and quantum effects are emerging that affect both the manufacturing process and the functionality of today’s microelectronic systems-on-chip. Spintronic devices that take advantage of the electron spin are widely seen as the most promising solutions to circumvent the CMOS technology scaling threats. Given that they combine non-volatility with radiation immunity, speed, low power consumption, and quasi-infinite endurance, it is possible to use them in a wide variety of applications. In this chapter, spintronic phenomena, technology and hybrid (CMOS/MRAM) devices are presented as well as their use in processor domain (to replace parts of the memory hierarchy), hybrid logic, and reconfigurable computing.

Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs

In this paper both theoretical and experimental comparative performance analysis of several binary adder architectures is performed. Also, one modified carry-bypass technique for adder performance improvement is presented. When applying simple unit-gate theoretical model for area and delay estimation it has been shown that logarithmic delay architectures (carry-lookahead and prefix adders) are the fastest but the most hardware demanding. On the other hand, the implementations in modern Virtex-6 general purpose FPGAs witness that here presented carry-bypass technique is the best tradeoff for such devices in terms of area, speed and power consumption. Presented results can be considered as a valuable resource in the selection of the most appropriate adder topology that will be used to implement a given arithmetic operation in a specified technology.