Raphael Martins Brum

High Performance SoC Design Using Magnetic Logic and Memory

As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view.

Trends on the application of emerging nonvolatile memory to processors and programmable devices

A number of non-volatile memory technologies (NVMs) emerged in the past years. They promise to cope with limitations of standard memory technologies, such as scalability and idle power consumption. Numerous logic circuits based on these emerging technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in this field. In the first part, this article provides a survey on the application of those memories to programmable devices. The second section is dedicated to the use of NVMs in the processors memory hierarchy, where we discuss potential applications based on a preliminary study we performed. Results were obtained using TAS-MRAM NVM technology.

Embedded MRAM for high-speed computing

As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.

Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions

In the last few years, spintronics has attracted the full attention of the scientific community for the synergy it provides to conventional complimentary metal-oxide-semiconductor (CMOS) devices (nonvolatility, infinite endurance, radiation immunity, increased density, and so on). Many hybrid (magnetic/CMOS) cells have been proposed which can store and process data in both electrical and magnetic ways. Such cells are mainly based on magnetic tunnel junctions (MTJs) and are suitable for use in magnetic random access memories (MRAMs) and reprogrammable computing (magnetic FPGAs, nonvolatile registers, processor cache memories, and so on). In this paper, we report the results of exhaustive energy-performance analysis of the set of hybrid cells recently published in the literature. We explore their limits in metrics of the required silicon area, robustness, read/write speed, and consumed energy. Two different mechanisms for writing non-volatile data stored in MTJs are applied to each hybrid cell: thermally assisted switching (TAS) and spin-transfer torque (STT). All the results were obtained through simulations in Cadence Spectre 7.2. For the CMOS part, we used 45 nm predictive transistor models whereas the MTJ part was simulated using the 120 nm × 120 nm TAS Spintec model and the 100 nm × 50 nm STT Spinlib model. The results presented here are a valuable resource for future designers of hybrid devices if they need to select an appropriate hybrid cell for a target application.

Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing

The main objective of this paper is to give an overview of different hybrid MRAM/CMOS cells to use in the context of reconfigurable computing. The way to convert magnetic information into an electrical one is not unique and we propose to compare different kind of hybrid cells. These hybrid cells can be used to define structures as Look-up Table, configuration memory point, Flip-flop and other basic elements needed to define programmable logic. Even if these cells were designed for the TAS (Thermally Assisted Switching) MRAM technology, it is possible to adapt them to more advanced technologies such as STT (Spin Transfer Torque).

Embedded memory hierarchy exploration based on magnetic RAM

SRAM, DRAM and FLASH are the three main employed technologies in design of on-chip processor memories. However, manufacturing constraints for this technologies in the most advanced nodes compromises further evolution. MRAM (Magnetic memory) presents itself as an attractive alternative for these technologies, as it has reasonable timing and power characteristics. Last results in the state of the art demonstrate that MRAM access time is can be less than 5ns and read/write energy per bit in same order of magnitude as SRAM, also it can evolve with the manufacturing process. One important feature of MRAM is the non-volatility, allowing to define new instant on/off policies and mainly optimizing leakage current. In this paper we demonstrate how MRAM can be used into memory hierarchy of embedded systems. The main objective is to demonstrate the interest to use MRAM for Level-1 & 2 cache and to better understand the architectural choice in order to minimize the impact of the higher write latency of MRAMs.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

Ater decades of continued scaling to the beat of Moores law, it now appears that conventional silicon based devices are approaching their physical limits. In todays deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Potential applications based on NVM emerging technologies

Energy efficiency is a critical figure of merit for battery-powered applications. Todays embedded systems suffer from significant increase of power consumption essentially due to a high leakage current in advanced technology node. A significant portion of the total power consumption is spent into memory systems because of an increasing trend of embedded volatile memory area among the building components in System-on-Chips (SoCs). That is why new Non-Volatile Memory (NVM) technologies are considered as a potential solution to solve the energy efficiency issue. Among these NVM technologies, Magnetic RAM (MRAM) is a promising candidate to replace current memories since it combines non-volatility, high scalability, high density, low latency and low leakage. This paper explores use of MRAM into a memory hierarchy (from cache memory to register) of a processor-based system analyzing both performance and energy consumption.

Spintronic Memory-Based Reconfigurable Computing

Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing.

Logic Circuits Design Based on MRAM: From Single to Multi-States Cells Storage

In recent years, conventional silicon-based high-speed computing circuits became increasingly power-hungry due to the leakage currents and accelerated data traffic. Furthermore, numerous short-channel and quantum effects are emerging that affect both the manufacturing process and the functionality of today’s microelectronic systems-on-chip. Spintronic devices that take advantage of the electron spin are widely seen as the most promising solutions to circumvent the CMOS technology scaling threats. Given that they combine non-volatility with radiation immunity, speed, low power consumption, and quasi-infinite endurance, it is possible to use them in a wide variety of applications. In this chapter, spintronic phenomena, technology and hybrid (CMOS/MRAM) devices are presented as well as their use in processor domain (to replace parts of the memory hierarchy), hybrid logic, and reconfigurable computing.