Boon Yong Ang

NiSi Polysilicon Fuse Reliability in 65-nm Logic CMOS Technology

The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65-nm logic complimentary metal-oxide-semiconductor technology were studied. Under optimal programming conditions, high postprogram resistance can be achieved. These well-programmed fuses showed good data retention under unbiased temperature stress test. In order to avoid read disturb of unprogrammed fuses, the read current has to be kept below the threshold for silicide electromigration.

Characterization of Silicided Polysilicon Fuse Implemented in 65nm Logic CMOS Technology

NiSi electrically programmable fuses (eFUSE) were fabricated and investigated using 65 nm logic CMOS technology. The optimization of fuse program was achieved by analyzing electrical and physical responses of fuse bits for various conditions. Controlled electromigration of Ni during fuse program was identified as a key factor in achieving reliably high post-program fuse resistance.

NiSi Polysilicon Fuse Reliability in 65nm Logic CMOS Technology

The programming characteristics and reliability of NiSi polysilicon fuse fabricated using 65nm logic CMOS technology were studied. Under optimal programming conditions, high post-program resistance can be achieved. These well programmed fuses showed good data retention, capable of meeting the operating lifetime requirement of most applications

On-die thermal evaluation system

Thermal management of semiconductor chips has become a very critical topic in the industry. In this paper, we present a creative way of designing and using a versatile package-level thermal evaluation vehicle. The topic of thermal management in general and the example of the evaluation tool described in this paper are very relevant to the academic circles too. This paper describes the architecture, implementation, details of operation, programming aspects and usage model of a silicon chip designed as a thermal evaluation tool. This chip was fabricated in 0.18u technology, packaged and characterized. It has a simple implementation and is easy to program, yet has substantial thermal evaluation capabilities. This is an internal tool meant for evaluating our chip architecture, floorplan, packaging & cooling solutions. However, the concept of this thermal chip is applicable for the evaluation of a very wide range of products.