Myongseob Kim

Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention. Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents the reliability results as well as micro-bump resistance data. In addition, preconditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA. Furthermore, this paper details the outstanding TSV Keep-Out-Zone study (KOZ) for an active silicon interposer and the effect of TSV stress on transistor electron and hole mobility. Finally, an advanced thermal study of TSV interposer technology is presented to cool down a high-performance 28nm logic die (thousands of micro-bumps) that is mounted on a large silicon interposer with Cu through silicon via. Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures.

Reliability evaluation of an extreme TSV interposer and interconnects for the 20nm technology CoWoS IC package

TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. This paper presents the development of an extreme TSV interposer technology for three 23 × 14mm die slices that are mounted on a 25 × 45mm silicon interposer with Cu through silicon via. Interposer stitching is achieved either by real lithography stitching of 2 die slices or assembly of 2 adjacent dies (either identical or 2 different photo shots without stitching) together with connections through top dies. The low-k chip is a 20nm chip with total of 375,000 micro-bumps. The silicon interposer is 100um thick, and is mounted on a 55 × 55mm substrate through 30,000 C4 bumps. The substrate has 2892 BGA balls. 3D thermal-mechanical modeling and simulation for the FPGA package with TSV interposer have been performed. The FPGA samples have been subjected to thermal cycling and HTS tests. Effects of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated and measured. Several DOEs have been performed to optimize design and material selection in order to have a reliable 20nm FPGA silicon interposer package that has acceptable warpage/coplanarity, and passes 1000TCB and HTS 1000hrs without any failure or void being seen in low-k, micro bumps and C4 bumps. Furthermore, challenges in manufacturing, handling and reliability of this highly rectangular interposer are detailed. Finally, board level test data is presented to show reliability of BGA balls for this 55 × 55mm package.

Assembly process qualification and reliability evaluations for heterogeneous 2.5D FPGA with HiCTE Ceramic

This paper presents results for assembly and reliability evaluations performed while developing a first of its kind heterogeneous 2.5D HiCTE Ceramic Field Programmable Gate Array (FPGA) package. The heterogeneous device discussed here is a three dimensionally stacked FPGA device integrated with a 28G Transceiver die using a passive interposer. Several thousands of micro bumps are used for making connections between the FPGA die slices and the 28G transceiver through a passive interposer. Such heterogeneous integration enables ultra-high inter-die bandwidth and capacity at very low power that are essential for meeting the growing demands in the communication space. Also, it helps in achieving a much lower latency. The selection of ceramic substrates makes this three dimensional stacking very unique as its behavior at high temperature is very different from its organic counterparts. The Assembly test vehicles comprised of two 28nm FPGA Die and one 28nm Transceiver Die, all stacked side by side on a 25 mm × 20mm interposer. The FPGA and Interposer assembly was stacked on a 35mm × 35mm Ceramic Substrate with 180μm pitch C4 bumps. Assembly evaluations were primarily focused on qualifying various materials and assembly processes to enable a heterogeneous stacked silicon assembly on a ceramic substrate. Micro bump joint quality, assembly yield, component level reliability and board level reliability have been used as the key gating items for this process qualification study. Two different assembly processes, namely thermo-compression (TC) bonding and mass reflow, were compared during this evaluation. Component and board level reliability evaluations were carried out for various assembly and material combinations. The assembled units were subjected to Level 4 (L4) preconditioning test followed by -55°C to 125 °C thermal regimes and tested for functionality to monitor the component level reliability. Board level studies were conducted at 0°C to 100 °C using daisy chain substrates. The resistance of the BGA chain was used for monitoring the board level reliability. The results of this evaluation have clearly demonstrated a strong interaction between the materials, assembly process and reliability. The choice of the assembly process was observed to have a significant impact on the micro bump joint quality. However, the choice of the assembly process itself was dependent on the selection of the various assembly materials including underfill, flux, substrate type, surface finish, lid thickness and die thickness. The assembly process and material set together influenced the component and board level reliability significantly.

3DIC developments for high yield and reliability manufacturing

3D-IC has been recognized as one of the technology solutions from More than Moore. Xilinxs 3D-IC FPGA has been well adopted by the industry since the first Virtex®-7 2000T introduced in 2011. In particular recently, data center requires large volume of 3D-IC for its applications. To fulfill the high demand effectively the best way is to provide the high yield and reliability 3D-IC product supply. The authors would like to share Xilinxs 3D-IC development experiences by means of launching process learning vehicles, pursuing early stages reliability assessment, and optimizing the process baseline. All the development efforts paved the foundation for a robust production line. At the end, the potential future 3D-IC technology challenges are outlined.