Bora Baloglu

Coreless substrate with asymmetric design to improve package warpage

Coreless substrates have been used in more and more advanced package designs for their benefits in electrical performance and reduction in thickness. However, coreless substrate causes severe package warpage due to the lack of a rigid and low CTE core. In this paper, both experimental measured warpage data and model simulation data are presented and illustrate that asymmetric designs in substrate thickness direction are capable of improving package warpage when compared to the traditional symmetric design. A few asymmetric design options are proposed, including Cu layer thickness asymmetric design, dielectric layer thickness asymmetric design and dielectric material property asymmetric design. These design options are then studied in depth by simulation to understand their mechanism and quantify their effectiveness for warpage improvement. From the results, it is found that the dielectric material property asymmetric design is the most effective option to improve package warpage, especially when using a lower CTE dielectric in the bottom layers of the substrate and a high CTE dielectric in top layers. Cu layer thickness asymmetric design is another effective way for warpage reduction. The bottom Cu layers should be thinner than the top Cu layers. It is also found that the dielectric layer thickness asymmetric design is only effective for high layer count substrate. It is not effective for low layer count substrate. In this approach, the bottom dielectric layers should be thicker than the top dielectric layers. Furthermore, the results show the asymmetric substrate designs are usually more effective for warpage improvement at high temperature than at room temperature. They are also more effective for a high layer count substrate than a low layer count substrate.

Cu Pillar flip chip assembly: Chip attach process failure mode study

An experiment is conducted to study failure mechanism during flip chip attach process for Cu Pillar bumped Si device that uses mass reflow assembly technology. A three-leg design of experiment (DOE) is conducted, which includes two UBM sizes, two different Cu pillar height, and with / without polyimide option to collect basic failure information. Finite element software is used to correlate the failure mode and identify the Si - Cu pillar bump - substrate interactions. Based on the experiment and finite element analysis results, a simple shallow beam mechanical model was recommended to be a basic start point of Cu Pillar flip chip assembly technology application. Results are discussed in details.

SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages

Wafer Level Chip Scale Packaging (WLCSP) designs, including Wafer Level Fan-Out (WLFO) technologies, are gaining more and more applications for next generation small and thin devices. Since the WLCSP and WLFO packages are mounted directly on the motherboard without a substrate as a buffer, the large coefficient of thermal expansion (CTE) mismatch between the silicon die and the motherboard makes the temperature cycle board level reliability (BLR) of WLCSP and WLFO a tremendous challenge, especially for large body sizes. Currently, a tin (Sn)-silver (Ag)-copper (Cu) solder alloy such as SAC405 is commonly used in WLCSP and WLFO designs, but it has difficulty meeting the board level reliability when the footprint exceeds a certain size. As a result, a new type of solder alloy, SACQ, has been developed in recent years to enhance BLR performance. However, there is little published reliability data of how this new SACQ solder performed in actual package applications. There is also lack of a BLR life prediction model for SACQ solder, unlike the other typical eutectic or leadfree solders. In this paper, the board level temperature cycle reliability of SACQ solder is tested with various WLCSP and WLFO packages configurations. The failure modes associated with SACQ solder are evaluated in detail as well. The temperature cycle performance of SACQ solder is also compared to SAC405 solder, and shows significant improvement consistently over all the packages tested. In addition to the empirical study, a BLR life prediction model for SACQ is also developed based on finite element model (FEM). The required SACQ creep material properties, finite element model setup, damage indicator selection, and life prediction model correlation are all described with details in the paper.

Electrical and Thermal Simulation of SWIFT (TM) High-Density Fan-Out PoP Technology

The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor (AP) and dedicated memory has become increasingly complex. Smartphones and tablets have become virtual streaming devices requiring low power, high bandwidth memory (HBM). For quality, high-speed video and multi-tasking applications, the memory interface to the AP must have superior signal integrity to minimize crosstalk and insertion/return losses. In addition, the thermal management of the processor must allow the maximum clock speed and duty cycle for high-performance applications. Finally, to conserve battery life for the mobility device, the power distribution to the processor must be as efficient as possible. This creates a significant challenge for the semiconductor packaging industry to meet these demanding requirements for smartphone and tablet products. This paper introduces a leading-edge high-density fan-out (HD-FO) semiconductor packaging technology that addresses the need for higher levels of integration and improved electrical and thermal performance for mobile applications. This new innovative technique, called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging, leverages the fine feature size and thin-film circuit patterning capabilities of wafer-level packaging. In addition, thin-film dielectric photolithography and pattern plating provides a significant reduction in package z-height, which is critical for advanced mobile devices. By incorporating a redistribution layer (RDL)-first/chip-last process flow, there is also an opportunity for yield optimization and cycle-time reduction. This work compares the electrical and thermal modeling results between a conventional Package-on-Package (PoP) and HD-FO SWIFT devices. The results reveal a highly integrated PoP structure with exceptional electrical, mechanical, and thermal performance benefits – compared to conventional organic laminate-based technologies – to meet the growing need for high-performance mobile applications.