Miguel Jimarez

Study of FC M BGA with low CTE core substrate

Amkors FCMBGA, flip chip package based on transfer molding for high performance device was developed and introduced to industry in 2008[1,2]. During the molding process, bump deformation was not significant, and voids were not observed under flip chip die. Coplanarity with a low Coefficient of Thermal Expansion, CTE, substrate construction was similar to a single piece lidded package construction. Coplanarity at high temperature did not change significantly with low CTE substrate compared to standard substrates. The flip chip package with molding passed reliability test such as Moisture Resistance Testing, MRT, and Thermal Cycling, TC 1500 cycles. No delamination or cracks were observed.

Development of large die fine pitch flip chip BGA using TCNCP technology

Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.

Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications

With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently, it is important to place memories as close as possible to ASICs. Standard Printed Circuit Board (PCB) design rules make it difficult to place several memories very close to ASICs, and PCBs are already densely populated. Consequently, there are two prevailing technologies that are used to increase density: Through Silicon Vias (TSVs) or System-in-Package (SiP) modules. TSVs are still in early stages of development, whereas smaller SiP modules have already been used in Networking [1, 2]. In this study, we outline an innovative SiP module solution: Implementation of a very large (90 × 90 mm) SiP module with 14 packaged DDR3 memories and 1 large flip low K chip ASIC mounted on a common Ball Grid Array (BGA) substrate. This is likely the largest organic BGA module ever built. Finite Element Analysis was performed to estimate the optimal stiffener and lid parameters for minimal warpage. Complete substrates were assembled with key metrics measured at each step of the assembly process. Excellent coplanarity was achieved in the assembly process. The SiP modules were then mounted on PCBs and the board level assembly process characterized. The modules were successfully mounted on the PCBs. The procedures and key learnings from this evaluation will be outlined in this study.

Robust Underfill Selection Methodology for Flip Chip

Underfill is one of the crucial materials in flip chip (FC) packages. The role of underfill is not only to protect the solder bumps but to minimize package warpage, and to protect the fragile low k dielectric at end of line (EOL), moisture resistance test (MRT), and temperature cycle B (TCB) conditions. As packages move towards green products, the complexity of selecting a good underfill increases. The interaction of high Pb or eutectic solder with the underfill is different than that of Pb free solder. Moreover Pb free solder behavior for FC bumps is just being explored in the literature. Besides Pb free solder, other parameters like die passivation, bump height and pitch, under bump metallurgy (UBM) metallization, and package substrate are also extremely important for underfill selection. As the design of the package continues to change smaller package, tighter bump pitch and thinner core and build up (BU) layers, all of these parameters are directly related to package reliability. Sometimes an underfill good for a smaller die, body size, taller bump height, and pitch doesn’t necessarily mean it will be appropriate for a bigger die with larger body, and tighter bumps. So there are lots of variables in the package that directly affect the reliability. A good underfill should have very good adhesion between underfill and die passivation at room temperature, and moderate adhesion at underfill Tg. Adhesion properties are solely depend on chemistry of the underfill. Therefore to determine a good underfill for a bigger die and body size, we need to have a sequential selection methodology. In this paper a sequential selection methodology is used to eliminate the unsuccessful underfill candidates and select the best one which comfortably satisfies the requirements for all different solder alloys, and a wider range of package geometries. Important selection criteria including underfill workability issues and modeling data are also discussed.Copyright

Lead Free Flip Chip Reliability for Various Package Types

Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCm BGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCm BGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application.© 2011 ASME

New Robust Process Improvement for BGA Solder Ball Attach First Pass Yield

In BGA package assembly, the solder ball attach process is one of the yield off points that impacts the overall product yield and cycle time because of the need to rework. From the beginning of BGA product manufacturing the race to achieve high solder ball attach yields has spurned various ball attach technology from flux printing to flux pin transfer, a multitude of flux formulations by various flux suppliers, improvement in solder ball pad finishes by substrate suppliers, and many other process improvement iteration. Today, the most popular ball attach technology in the industry is the use of pin transfer using tacky flux on solder on BGA pad (SOPBGA), Imm Sn, CuOSP, and ENIG Yet, the solder ball attach process continues to suffer missing balls, joined balls, and bridging balls, impacting the overall cycle time due to rework. This study shows the use of dippable paste, a novel ball attach material replacing flux thats compatible with pin transfer equipment technology and which pushes the first pass yield to 100%, virtually eliminating rework and could potentially reduce manufacturing cycle time. Dippable paste has been used mostly in package-on- package technology but most formulations are no-clean. A new water-soluble formulation was successfully prepared and applied to normal pin transfer ball attach process for the first time. The solder powder in the dippable paste improved wettability onto the pad finish. Results showed 100% first pass yield on FCBGA samples with SOPBGA, Imm Sn, ENIG, and CuOSP pad finishes. It also showed comparable coplanarity, solder ball height, solder ball diameter, solder ball shear, solder ball pull, and x-y pitch values with flux process. The robustness of the process is confirmed with perfect first pass yield even on poor surface conditions.