Brad Eichelberger

32nm Overlay Improvement Capabilities

The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control. Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning lithography is an approach thats being considered for 32 and below, but it creates very strict demands for overlay performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in extremely tight tolerances for overlay error and scanner capabilities. The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node. Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of current scanner performance and project the anticipated improvements from our new modeling approach. Since the new modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of such approach.

Simultaneous dose and focus monitoring on product wafers

As the design rules shrink below 130nm it will become increasingly important to monitor and control focus and dose in-line, on product wafers to maintain the ever-decreasing process window. On process layers today, it is not uncommon to see focus related errors equaling between 50-100nm in magnitude. Today these errors go undetected and CD changes are typically corrected by making a dose correction to the exposure tool. However, corrections using dose can lead to significantly smaller process latitude and therefore, products out of spec. Using a technique that was first developed by Christopher Ausschnitt at IBM Microelectronics it is possible to monitor focus and dose on production layers with a single compact target. Extending this technology on an advanced optical tool allows for precise measurements of focus and dose errors. This paper will describe the methodology of inline focus and dose monitoring using this technique on 130nm process technology with an outlook on the expectations for future nodes. Results, including focus and dose sensitivity from multiple process steps on production wafers will be shown.

Litho cell control using MPX

Optimal lithographic process control involves a closely coupled combination of test wafer and product wafer characterization. It has been shown in previous work that MPX (Monitor Photo Excursion) optical technology for line-end-shortening metrology of focus and dose provides reliable and low cost product monitor solution. In this work we apply MPX technology to litho cell monitor and control on test wafers. Focus-exposure matrix (FEM) wafers are measured and analyzed automatically on a routine basis. Process window parameters are tracked over time by scanner, including spatial analysis of results across the scanner field such as tilt and curvature. Improvements in litho cell control are discussed.

Edge die focus-exposure monitoring and compensation to improve CD distributions

As design rules shrink and process windows become smaller, it is increasingly important to monitor exposure tool focus and exposure in order to maximize device yield. Economic considerations are forcing us to consider nearly all methods to improve yield across the wafer. For example, it is not uncommon in the industry that chips around the edge of the wafer have lower yield or device speed. These effects are typically due to process and exposure tool errors at the edge of the wafer. In order to improve yield and chip performance, we must characterize and correct for changes in the effective focus and exposure at the edge. Monitoring focus and exposure on product wafers is the most effective means for correction, since product wafers provide the most realistic view of exposure tool interactions with the process. In this work, on-product monitoring and correction is based on optical measurement using a compact line end shortening (LES) target that provides a unique separation of exposure and focus on product wafers. Our ultimate objective is indirect CD control, with maximum yield and little or no impact on productivity.

Yield loss in lithographic patterning at the 65nm node and beyond

Parametric yield loss is an increasing fraction of total yield loss. Much of this originates in lithography in the form of pattern-limited yield. In particular, the ITRS has identified CD control at the 65nm technology node as a potential roadblock with no known solutions. At 65nm, shrinking design rules and narrowing process windows will become serious yield limiters. In high-volume production, corrections based on lot averages will have diminished correlation to device yield because APC systems will dramatically reduce error at the lot and wafer levels. As a result, cross-wafer and cross-field errors will dominate the systematic variation on 300mm wafers. Much of the yield loss will arise from hidden systematic variation, including intra-wafer dose and focus errors that occur during lithographic exposure. In addition, corollary systematic variation in the profiles of critical high-aspect-ratio structures will drive requirements for vertical process control. In this work, we model some of the potential yield losses and show how sensitive focus-exposure monitors and spectroscopic ellipsometry can be used to reduce the impact of hidden error on pattern limited yield, adding tens of millions of dollars in additional revenue per factory per year.