Kevin M. Monahan

Design and process limited yield at the 65-nm node and beyond

Immersion lithography at 193nm has emerged as the leading contender for critical patterning through the 32nm technology node. Super-high NA, along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.

Enabling Double Patterning at the 32nm Node

Most semiconductor manufacturers expect 193 nm immersion lithography to remain the dominant patterning technology through the 32 nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32 nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss interim solutions for control of double patterning lithography (DPL).

Enabling DFM and APC strategies at the 32 nm technology node

Most semiconductor manufacturers expect 193 nm immersion lithography to remain the dominant patterning technology through the 32 nm technology node. Even now, the interaction of more complex designs with shrinking process windows is severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multivariate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. In this work, we discuss new and innovative process metrics, including virtual metrology, that will be needed for yield at the 32 nm technology node.

Yield impact of cross-field and cross-wafer CD spatial uniformity: collapse of the deep-UV and 193 nm lithographic focus window

The 0.13 /spl mu/m semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures as small as 100 nm, creating a demand for sub-10 nm gate linewidth control. Linewidth variation consists of cross-chip, cross-wafer, cross-lot, and run-to-run components. In this work, we explore spatial dependencies across the lithographic field due to reticle error and across the wafer due to wafer and chuck nanotopography. Both sources of spatial variation can cause collapse of the lithographic focus window near the limits of resolution, resulting in CD excursions for gate structures in high-performance microprocessors. Our work supports the contention that photolithography-induced defects may become the primary source of yield loss for the 0.13 /spl mu/m generation and beyond.

Enabling immersion lithography and double patterning

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss some interim solutions for control of double patterning lithography (DPL), as well as some spacer-etch alternatives. We conclude with focus-exposure data showing some potential challenges for pitch-splitting strategies implemented in the context of immersion lithography.

Defects and metrology of ultrathin resist films

Defectivity in spin-coated, but unpatterned ultrathin resist (UTR) films (<EQ 1000 Angstrom) was studied in order to determine whether defectivity will present an issue in EUV (13.4-nm) and 157-nm lithographic technologies. These are the lithographic regimes where absorption issues mandate the use of ultrathin resists. Four resist samples formulated from the same Shipley UV6 polymer batch and having the same polymer molecular weight properties but different viscosities, were spin-coated at spin speeds ranging from 1000 to 5000 RPM on a production-grade track in a Class 1 pilot line facility. Defect inspection was carried out with KLA SP1/TBI tool, while defect review was carried out with JEOL 7515 SEM tool and KLA Ultrapointe Confocal Review Station (CRS) Microscope. The results obtained are related to the physical properties of the resist polymers, as well as to spin coating parameters. Also, the results of the defect inspection, review, characterization, and pareto are compared to those obtained on baseline thick resists (>= 3500 Angstrom) processed under similar condition as the ultra-thin resists. The results show that for a well-optimized coating process and within the thickness range explored (800 - 4200 Angstrom), there is no discernible dependence of defectivity on film thickness of the particular resists studied and on spin speed. Also assessed is the capability of the current metrology toolset for inspecting, reviewing, and classifying the various types of defects in UTR films.

Application of statistical metrology to reduce total uncertainty in the CD-SEM measurement of across-chip linewidth variation

Statistical metrology can be defined as a set of procedures to remove systematic and random gauge error from confounded measurement data for the purpose of reducing total uncertainty. We have applied these procedures to the determination of across-chip linewidth variation, a critical statistic in determining the speed binning and average selling price of advanced microprocessors, digital signal processors, and high-performance memory devices. The measurement data was obtained from tow sources: a high- throughput CD-SEM and an atomic force microscope. We found that the high-throughput of SEM permitted the additional measurements required for statistical metrology and heterogeneous gauge matching.

Enabling DFM and APC strategies with advanced process metrics

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. If this remains the case, the interaction of more complex designs with shrinking process windows will severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multi-variate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. In this work, we discuss new and innovative process metrics, including simulation-based virtual metrology, that will be needed for yield at the 32nm technology node.

Microeconomics of yield learning and process control in semiconductor manufacturing

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

Microeconomics of Process control in semiconductor manufacturing

Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.