Braden Phillips

Fast Decimal Floating-Point Division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

Minimal weight digit set conversions

We consider the problem of recoding a number to minimize the number of nonzero digits in its representation, that is, to minimize the weight of the representation. A general sliding window scheme is described that extends minimal binary sliding window conversion to arbitrary radix and to encompass signed digit sets. This new conversion expresses a number of known recoding techniques as special cases. Proof that this scheme achieves minimal weight for a given digit set is provided and results concerning the theoretical average and worst-case weight are derived.

A decimal carry-free adder

Recently, decimal arithmetic has become attractive in the financial and commercial world including banking, tax calculation, currency conversion, insurance and accounting. Although computers are still carrying out decimal calculation using software libraries and binary floating-point numbers, it is likely that in the near future, all processors will be equipped with units performing decimal operations directly on decimal operands. One critical building block for some complex decimal operations is the decimal carry-free adder. This paper discusses the mathematical framework of the addition, introduces a new signed-digit format for representing decimal numbers and presents an efficient architectural implementation. Delay estimation analysis shows that the adder offers improved performance over earlier designs.

Fast Scaling in the Residue Number System

A new scheme for precisely scaling numbers in the residue number system (RNS) is presented. The scale factor K can be any number coprime to the RNS moduli. Lookup table implementations are used as a basis for comparisons between the new scheme and scaling schemes from the literature. It is shown that new scheme decreases hardware complexity compared to previous schemes without affecting time complexity.

Implementing 1,024-bit RSA exponentiation on a 32-bit processor core

This paper describes how long-wordlength (1024-bit) modular exponentiation may be implemented on a standard 32-bit microprocessor core with a total execution lime of under 1 second. The design does not use a long-wordlength arithmetic co-processor. Instead all arithmetic operations are reduced to 32-bit additions, subtractions and binary shifts, and the processor is augmented with a small hardware enhancement to significantly accelerate accumulation of shifted multi-precision numbers. Target performance is achieved by trading fast arithmetic hardware for extra RAM, to facilitate pre-computation of digit multiples and powers. Signed sliding window algorithms are introduced for exponentiation, multiplication and reduction operations, and attention is paid to the integration of enhanced security features such as blinding and verification.

Arithmetic data value speculation

Value speculation is currently widely used in processor designs to increase the overall number of instructions executed per cycle (IPC). Current methods use sophisticated prediction techniques to speculate on the outcome of branches and execute code accordingly. Speculation can be extended to the approximation of arithmetic values. As arithmetic operations are slow to complete in pipelined execution an increase in overall IPC is possible through accurate arithmetic data value speculation. This paper will focus on integer adder units for the purposes of demonstrating arithmetic data value speculation.

A MIPS R2000 implementation

Thirty-four undergraduates implemented a MIPS R2000 processor for an introductory CMOS VLSI design course. This included designing a microarchitecture in Verilog, developing custom PLA generation and ad-hoc random testing tools, creating a standard cell library, schematics, layout, and PCB test board. The processor was fabricated by MOSIS on an AMI 0.5-micron process, included 160,000 transistors, and ran at 7.25 MHz.

Estimating adders for a low density parity check decoder

Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.

Elliptic curve digital signature algorithm over GF(p) on a residue number system enabled microprocessor

We describe a residue number system (RNS) implementation of the 192-bit elliptic curve digital signature algorithm over GF(p). It uses a Tensilica Xtensa LX2.1 microprocessor core with hardware extensions to improve the performance of RNS operations. The low power and small area of the enhanced Xtensa LX2.1 core make it suitable for smart cards. This implementation is the first to use the RNS for elliptic curve cryptography on a sequential microprocessor. The RNS-enabled microprocessor performs a 192-bit point multiplication in approximately 2 million clock cycles, a performance that compares well to other minimally enhanced elliptic curve cryptography implementations.

An RNS-Enhanced Microprocessor Implementation of Public Key Cryptography

This paper presents a new residue number system implementation of the RSA cryptosystem. The system runs on a low-area, low-power microprocessor that we have extended with hardware support for residue arithmetic. When compared against a baseline implementation that uses non-RNS multi-precision methods, the new RNS implementation executes in 67.7% fewer clock cycles. The hardware support requires 42.7% more gates than the base processor core.