Bradley D. Herrman

Embedded capacitor in power distribution design of high-end server packages

This paper investigates the role of embedded capacitors in the enablement of future high speed digital systems. Present and future chip core and off-chip clock frequencies impose high demands on the design of the power and signal distribution systems. This requires careful and more effective design techniques at the electronic packaging level to mitigate the increasing power and signal noise jitter components. Embedded capacitors present opportunities for increased performance, increased functionality, increased package density and decreased cost. It is shown that embedded capacitor provides efficient signal current return path which in turns yields a significant reduction of signal crosstalk noise and simultaneous switching noise (SSN). This allows for tighter signal spacing ground rules and a reduced package cost

Delay analysis using FDTD for source synchronous interfaces

This paper investigates delay and current return effects utilizing a parallel conformal finite difference time domain (PFDTD) method [Wenhua Yu, 2003]. Methodology, modeling, and integration to system level simulation for several interconnect structures are presented.