Erdem Matoglu

Finite-difference modeling of noise coupling between power/ground planes in multilayered packages and boards

Multilayered packages and boards, such as high performance server boards, contain thousands of signal lines, which have to be routed on and through several layers with power/ground planes in between. There can be noise coupling not only in the transversal direction through the power/ground planes in such a structure, but also vertically from one plane pair to another through the apertures and via holes. In addition, the continuous increase in power demand along with reduced Vdd values results in significant current requirement for the future chips. Hence, the parasitic effects of the power distribution system become increasingly more critical regarding the signal integrity and electromagnetic interference properties of cost-effective high-performance designs. We present a multilayer finite-difference method (M-FDM), which is capable of characterizing such noise coupling mechanisms. This method allows considering realistic structures, which would be prohibitive to simulate using full-wave simulators

Digital and RF integration in system-on-a-package (SOP)

The Packaging Research Center (PRC) is developing system-on-a-package (SOP) technology, as a complimentary alternative to SOC, as the fundamental building block for next generation convergent systems with computing, telecom and consumer capabilities with data and voice. Any systems of this nature have to provide not only high-speed digital, but also high bandwidth optical, analog, RF and perhaps MEMS functions. The SOP technology being pursued at PRC with embedded digital, optical and RF functions addresses this need, optimizing the IC and the package for functions, performance, cost, size and reliability. The PRC is developing this complimentary alternative to SOC using a three tier strategy consisting of fundamental research innovations, enabling technology developments and system-level testbeds. Individual digital, optical and RF testbeds have been developed to enable the integration of novel packaging technologies like embedded passive and optical components, high density global interconnections and wafer level flip-chip assembly. A phased system testbed is being evolved from these three testbeds to develop new SOP convergent system platforms for a digital/optical/RF system implementation. This paper summarizes the latest PRC accomplishments in the development of SOP baseline processes and system testbeds and updates the progress from basic research and technology integration to system testbeds for SOP.

Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method

This paper presents a method for analyzing multilayered power distribution networks in the frequency domain. Using a two dimensional array of distributed RLCG circuits, multi-layered power distribution planes are represented. Each plane pair is connected by vias, which are modeled as partial self and mutual inductors. For the efficient computation of the power distribution impedances at specific points in the network, a multiinput and multi-output transmission matrix method has been used, which is much faster than Spice and reduces memory requirements. This method has been compared with the cavity resonator method simulated in Spice.

Statistical analysis and diagnosis methodology for RF circuits in LCP substrates

This paper presents the application of a fast and accurate layout-level statistical analysis methodology for the diagnosis of RF circuit layouts with embedded passives in liquid crystalline polymer substrates. The approach is based on layout-segmentation, lumped-element modeling, sensitivity analysis, and extraction of probability density function using convolution methods. The statistical analyses were utilized as a diagnosis tool to estimate distributed design parameter variations and yield of RF circuit layouts for a given measured performance. The results of statistical analysis and diagnosis were compared with measurement results of fabricated filters. Statistical methods were also applied for design space exploration to improve system performance, as well as estimation of yield and diagnosis of faults during batch fabrication.

Efficient statistical analysis and diagnosis of high speed source synchronous interfaces

The jitter and voltage margin of a source synchronous memory bus has been analyzed under various physical and operational conditions. Using sensitivity functions derived through linearly independent experiments, the statistical distribution of the performance has been computed. The sensitivity functions have also been utilized as a diagnosis tool to estimate the design parameters required to meet the performance specifications.

Statistical modeling of a multi-drop source synchronous bus

Using the source synchronous switching technique, high data rates can be achieved on the system board. When designing a source synchronous board, the goal is to minimize the variations in the differential delay between the data and strobe lines. This delay is often affected by jitter caused by power supply noise, cross talk, reflections and other signal integrity violations. This paper investigates the inter-relationships between electrical parameters in a printed circuit board to the physical manufacturing parameters for a source synchronous bus. Using sensitivity functions and statistical distributions of the physical parameters, the variations of the electrical parameters are computed. The correlation matrix between the electrical parameters can be used to understand the sensitivity of various electrical and physical parameters for the performance of the bus. This information can be used for redesigning boards by accounting for manufacturing variations.

Macromodeling of nonlinear transistor-level receiver circuits

In this paper, a modeling methodology for macromodeling transistor-level receiver circuits has been presented. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits, i.e., the input characteristics of the receivers. In this paper, a modeling methodology that addresses both the loading effect as well as the output characteristics of the receiver has been proposed. This modeling technique is simple, accurate, and has huge computational speed-up over transistor-level receiver circuits. To model the input characteristics of the receiver, spline function with finite time difference (SFWFTD) and recurrent neural network (RNN) modeling methods have been used. The output characteristics of the receiver are modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on some test cases and results show good accuracy and substantial speed-up compare to transistor-level receiver circuits. The proposed modeling technique has been extended to multiple ports to estimate sensitive effects like simultaneous switching noise (SSN) when multiple receivers are switching.

Macro-modeling of non-linear pre-emphasis differential driver circuits

Differential signaling has become important in high speed digital and mixed signal systems because of its numerous advantages over single-ended signaling. Differential signaling reduces effects like simultaneous switching noise (SSN), electro magnetic interference (EMI) and crosstalk coupling. Signal integrity (SI) and timing analysis using differential drivers is computationally exhaustive due to increased complexity in design that includes features such as pre-compensation and slew rate control. Therefore, accurate macro-modeling of differential driver circuits for a quality design is a huge challenge. In this paper, a modeling technique based on recurrent neural network (RNN) is proposed to model differential driver circuits with and without pre-emphasis. Good accuracy is obtained in the test cases shown for the proposed modeling methodology at minimum computational cost.

Design space exploration of high-speed busses using statistical methods

This paper presents an efficient statistical method to increase the data rate of local I/O bus. Parametric yield of the PCI-X has been computed at a higher data rate. Then yield loss at higher data rate has been recovered by making the most feasible and effective adjustments. Instead of full factorial signal integrity analysis, sensitivity relations and statistical distributions of signal integrity measures have been computed, which supply detailed information to designers and manufacturers.