Daniel N. De Araujo

Finite-difference modeling of noise coupling between power/ground planes in multilayered packages and boards

Multilayered packages and boards, such as high performance server boards, contain thousands of signal lines, which have to be routed on and through several layers with power/ground planes in between. There can be noise coupling not only in the transversal direction through the power/ground planes in such a structure, but also vertically from one plane pair to another through the apertures and via holes. In addition, the continuous increase in power demand along with reduced Vdd values results in significant current requirement for the future chips. Hence, the parasitic effects of the power distribution system become increasingly more critical regarding the signal integrity and electromagnetic interference properties of cost-effective high-performance designs. We present a multilayer finite-difference method (M-FDM), which is capable of characterizing such noise coupling mechanisms. This method allows considering realistic structures, which would be prohibitive to simulate using full-wave simulators

Statistical signal integrity analysis and diagnosis methodology for high-speed systems

This paper discusses an efficient statistical analysis methodology for system-level signal integrity analysis. In the proposed method, statistical variations of the design and operational parameters are mapped to system performance through simulations based on orthogonal Taguchi arrays. Using the sensitivity functions derived from these simulations, statistical distributions of the performance measures are computed. The sensitivity functions and probability distributions of the design parameters are utilized as a diagnosis tool to estimate the design parameters of a system for a given measured performance. The statistical methodology is applied for design space exploration to improve system performance. For demonstrating the concept, a source synchronous memory bus and a peripheral input-output (I/O) bus have been analyzed under design and operational variations.

Analysis of fully buffered DIMM interface in high-speed server applications

Processor, memory, and I/O are three important segments in todays high-speed server platforms. Doubling of processor speed almost every two years and recent advancements in processor performance by developments such as multi-core processing and simultaneous multi-threading (SMT) have resulted in an imbalance in the three segments. With the introduction of serial I/O technologies like PCI express and serial attached SCSI (SAS) as the industry standard, the I/O subsystem is keeping pace with processing advancements. However, in high-speed server applications, the memory capacity and throughput are becoming important issues. As the memory data rates increase to match the increasing processor speeds, multi-drop parallel bus limitations constrain the memory systems scalability. Therefore, result in failure to meet the memory capacity requirements of modern server and workstation applications. Because of the need for increased memory capacity to keep up with both processor and I/O improvements, the industry has opted for a new approach called fully buffered DIMM (FB-DIMM). FB-DIMM addresses both the scaling needs in terms of capacity and bandwidth requirements. In FB-DIMM technology, an advanced memory buffer (AMB) is added to each DIMM and the memory controller communicates with AMB in a daisy chained, point-to-point serial interface. This allows the memory channel to operate at higher data rates and support more connections. In this paper, electrical design characteristics of a FB-DIMM memory interface are analyzed in a high-end rack-mount and blade server application. Also, the next generation FB-DIMM interface in a production high-end server environment from a signal integrity perspective is discussed. Sensitivity analysis for the variations in electrical parameters

Efficient statistical analysis and diagnosis of high speed source synchronous interfaces

The jitter and voltage margin of a source synchronous memory bus has been analyzed under various physical and operational conditions. Using sensitivity functions derived through linearly independent experiments, the statistical distribution of the performance has been computed. The sensitivity functions have also been utilized as a diagnosis tool to estimate the design parameters required to meet the performance specifications.

Design methodology for multiple domain power distribution systems

High-speed digital devices require multiple voltage and frequency domains to accommodate the core logic and the input/output (I/O) circuitry for multiple interfaces. In addition, some of these interfaces are programmable to various speeds and signaling modes and they require multiple power supply voltages. These requirements create complex power delivery and signal distribution solutions. This paper proposes a design methodology for fast transient point of load (POL) power distribution architectures for microprocessors and fast switching logic. This paper presents an efficient power distribution system (PDS) design methodology that models the load, its point of load power converter, and the transporting system so that the entire system can be efficiently implemented in circuit simulation as a complete integrated setup for design optimization. Models for the voltage regulator module (VRM) and its transient response and stability, the active load with multiple power supply domains, and the power planes are discussed in detail. System voltage noise margin budgeting is also emphasized.

Analysis of Embedded Package Capacitors for High Performance Components

The ever increasing power requirements of processors and application specific integrated circuits (ASICs) impose stringent requirements on the design of power distribution networks (PDNs). This paper highlights a power analysis methodology and discusses the decoupling requirements of high performance components. The advantages of embedded package capacitors in core and I/O decoupling will be highlighted

Optical high speed symmetric multi-processor link implementation

High-end computing servers configured as symmetric multi-processor (SMP) systems rely on parallel high speed links for interconnection between the processors. With each new generation of processor, the bandwidth of the SMP link is increased. Wired copper cables are still the technology of choice for this application but with each increment in bandwidth, fiber optic interconnects become more competitive solution contenders. To obtain an early look at the issues facing fiber optics in the SMP application, two types of optical links, all-optical and hybrid-optical, were built and characterized in a real system. These links were evaluated in terms of cost, size, power dissipation, temperature rise, electrical interface, latency and bit error ratio (BER). In both implementations, an 8-way SMP system was successfully operated

Voltage regulator module noise analysis for high-volume server applications

This paper presents a methodology to analyze voltage regulator module (VRM) noise coupling problems in high-volume server applications. The technique is applied on a real engineering design. The comprehensive model includes irregular power shapes, decoupling capacitors, and dielectric and conductive loss. Irregular shaped power plane modeling is cross-checked with four separate methods to demonstrate accuracy.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

Modeling broadside coupled traces using equivalent per unit length (Eq PUL) RLGC model

Increases in printed circuit board (PCB) cost is leading to denser routing of high speed signal traces and this, in turn, is increasing the crosstalk among the traces. The crosstalk between the broadside coupled traces in adjacent layers is becoming an important factor to account for as the signal speeds increase. The coupling between parallel broadside coupled traces can be modeled using multi-conductor transmission line theory based on telegrapher equations using equivalent per-unit-length (Eq PUL) resistance, inductance, capacitance, and conductance (RLCG) matrices. The same approach is not applicable for the traces crossing at an arbitrary angle. A fast methodology to develop Eq PUL RLGC models that captures the coupling physics of broadside coupled traces crossing at an angle based on geometrical parameters of the stackup, and the dielectric material properties is proposed based on the idea presented in [1]. In this paper, validation of these equivalent models is done by estimating the crosstalk impact on eye opening at a specified bit error rate (BER) at different signal speeds and results are compared against full wave models.