Guido Gronthoud

Defect-based delay testing of resistive vias-contacts a critical evaluation

This defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment. Delay fault testing has uncertainty, or noise, in its attempt to detect defects that slow a signal. CMOS resistive vias and contacts were used as a delay defect target. Data were taken from a scan-based test chip (Veqtor) on the Philips 0.25 /spl mu/m technology. Methods to improve delay fault defect detection are given.

On hazard-free patterns for fine-delay fault testing

This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.

Vdd ramp testing for rf circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.

A novel stuck-at based method for transistor stuck-open fault diagnosis

While most of the fault diagnosis tools are based on gate level fault models, for instance the stuck-at model, many faults are actually at the transistor level. The stuck-open fault is one example. In this paper we introduce a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis. The method transforms the transistor level circuit description to a gate level description where stuck-open faults are represented by stuck-at faults, so that the stuck-open faults can be diagnosed directly by any of the stuck-at fault diagnosis tools. The transformation is only performed on selected gates and thus has little extra computational cost. This method also applies to the diagnosis of multiple stuck-open faults within a gate. Successful diagnosis results are presented using wafer test data and an internal diagnosis tool from Philips

Modeling Power Supply Noise in Delay Testing

Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and

A gate-level method for transistor-level bridging fault diagnosis

The paper addresses the issue of transistor-level bridging fault diagnosis. While most of the previous bridging fault diagnosis work focuses on the gate-level bridging faults, this method provides a solution to intra-gate bridging faults diagnosis for the first time. Instead of using any transistor level simulation tools, we develop a transformation technique that allows transistor-level bridging faults to be diagnosed by the commonly used gate-level bridging faults diagnosis tools. Real diagnosis results from Philips designs are presented

Stuck-open fault diagnosis with stuck-at model

While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the transistor level. The stuck-open fault is one of them. In this paper we introduce a stuck-open fault diagnosis method based on the stuck-at fault model. First we investigate how stuck-open faults show in the stuck-at diagnosis. Based on the stuck-at diagnosis result, a transformation method is used to represent stuck-open faults. This method transforms the transistor level circuit description to a gate level description so that the stuck-open faults can be diagnosed directly by any of the stuck-at fault diagnosis tools. After the transformation, all the stuck-open faults are fully diagnosed by FALOC, a gate level fault diagnosis tool from Philips.

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 /spl mu/m technology. The IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.

Extending gate-level diagnosis tools to CMOS intra-gate faults

A comprehensive solution to the intra-gate diagnosis problem, including intra-gate bridging and stuck-open faults is provided. The work is based on a local transformation technique that allows transistor-level faults to be diagnosed by the commonly available gate-level fault diagnosis tools without having to deal with the complexity of a transistor-level description of the whole circuit. Three transformations are described: one for stuck-open faults, one for intra-gate resistive-open faults and one for intra-gate bridging faults. Experimental work has been conducted at NXP Semiconductors using the NXP diagnosis tool – FALOC. A number of real diagnosis results from the wafer testing data including both stuck-open faults and intra-gate bridging faults have confirmed the effectiveness of this new method.

Reducing analogue fault-simulation time by using ifigh-level modelling in dotss for an industrial design

A crucial issue for using defect-oriented testing in analogue testing is how to reduce the massive faultsimulation time. One solution to this problem is to use high-level models in the fault simulation. However, the high-level model used in fault simulations has diferent requirements as compared to the high-level model normally used in IC design. This is because the behaviour of the faulty block is unknown and it is possible that it works totally diflerent from the fault-ffee one. In this paper, a new general structure of a high-level model with three stages is proposed. The approach has been applied to the RECEIVER block of an industrial chip. The fault simulations with this high-level model have been carried out with Dotss, an industrial analogue fault simulation and test optimisation tool based on defect-oriented testing. The results show that this kind of high-level models can work properly in fault simulations and effectively reduce the fault-simulation time.