Camelia Hora

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as Gate-Exhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design.

Diagnosis of Local Spot Defects in Analog Circuits

We present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study.

A novel stuck-at based method for transistor stuck-open fault diagnosis

While most of the fault diagnosis tools are based on gate level fault models, for instance the stuck-at model, many faults are actually at the transistor level. The stuck-open fault is one example. In this paper we introduce a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis. The method transforms the transistor level circuit description to a gate level description where stuck-open faults are represented by stuck-at faults, so that the stuck-open faults can be diagnosed directly by any of the stuck-at fault diagnosis tools. The transformation is only performed on selected gates and thus has little extra computational cost. This method also applies to the diagnosis of multiple stuck-open faults within a gate. Successful diagnosis results are presented using wafer test data and an internal diagnosis tool from Philips

Defect Oriented Testing for analog/mixed-signal devices

We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup of over 100x in the DOT process. Moreover, a number of methods are presented to improve the accuracy of this algorithm. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the analyzed production tests of the device can be reduced by at least 50%.

Diagnosis of Full Open Defects in Interconnecting Lines

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality

With test quality being an imperative, this paper presents a methodology on how to apply volume scan diagnosis - known from the field of yield learning - to the domain of test quality learning. Volume diagnosis allows to drastically accelerate the learning cycle. We give guidelines on how to improve test pattern generation strategies and try to answer which defects can be addressed deterministically with adequate fault models versus where probabilistic methods such as N-detect need be applied. The paper is based on a detailed analysis of scan diagnosis data from a production volume of well over one million devices of a 90 nm product.

Full Open Defects in Nanometric CMOS

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric CMOS technologies, the oxide thickness is reduced below a few tens of Aring causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic CMOS gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on predictive technology models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18 mum technology.

Extending gate-level diagnosis tools to CMOS intra-gate faults

A comprehensive solution to the intra-gate diagnosis problem, including intra-gate bridging and stuck-open faults is provided. The work is based on a local transformation technique that allows transistor-level faults to be diagnosed by the commonly available gate-level fault diagnosis tools without having to deal with the complexity of a transistor-level description of the whole circuit. Three transformations are described: one for stuck-open faults, one for intra-gate resistive-open faults and one for intra-gate bridging faults. Experimental work has been conducted at NXP Semiconductors using the NXP diagnosis tool – FALOC. A number of real diagnosis results from the wafer testing data including both stuck-open faults and intra-gate bridging faults have confirmed the effectiveness of this new method.

Defect Oriented Testing for Analog/Mixed-Signal Designs

In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.