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Dive into the research topics where Zhiyu Ru is active.

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Featured researches published by Zhiyu Ru.


IEEE Journal of Solid-state Circuits | 2009

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

Zhiyu Ru; Niels A. Moseley; Eric A.M. Klumperink; Bram Nauta

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.


international solid-state circuits conference | 2009

A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF

Michiel C. M. Soer; Eric A.M. Klumperink; Zhiyu Ru; F.E. van Vliet; Bram Nauta

Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited [1]. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core [2,3] for low conversion loss and low noise folding it is shown that it is possible to realize IIP3≫11dBm and NF≪6.5dB, i.e. a remarkably high SFDR≫79dB in 1MHz bandwidth over a decade of RF frequencies.


international solid-state circuits conference | 2008

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

Zhiyu Ru; Eric A.M. Klumperink; Bram Nauta

The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3rd and 5th harmonic mixing. An inverter-based RF-amplifier (RFA) drives a passive switched-capacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, second stage consists of I/Q DT mixers for downconversion and the third stage is a low-pass IIR filter. The chip fabricated in a 65nm CMOS process occupies an active area of 0.36mm2. The noise and linearity performances are competitive with those of continuous-time mixers at reasonable power consumption, which shows the feasibility of the proposed architecture for a practical receiver front-end.


IEEE Journal of Solid-state Circuits | 2010

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

Zhiyu Ru; Eric A.M. Klumperink; Bram Nauta

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation.


IEEE Journal of Solid-state Circuits | 2010

A 300–800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

Zhiyu Ru; Eric A.M. Klumperink; Carlos E. Saavedra; Bram Nauta

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.


international solid-state circuits conference | 2009

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Niels A. Moseley; Zhiyu Ru; Eric A.M. Klumperink; Bram Nauta

Wideband direct-conversion harmonic-rejection (HR) receivers for software-defined radio aim to remove or relax the pre-mixer RF filters, which are inflexible, bulky and costly [1,2]. HR schemes derived from [3] are often used, but amplitude and phase mismatches limit HR to between 30 and 40dB [1,2]. A quick calculation shows that much more rejection is wanted: in order to bring harmonic responses down to the noise floor (e.g. −100dBm in 10MHz for 4dB NF), and cope with interferers between −40 and 0dBm, an HR of 60 to 100dB is needed. Also in terrestrial TV receivers and in applications like DVB-H with co-existence requirements with GSM/WLAN transmitters in a small telephone, high HR is needed.


international symposium on circuits and systems | 2007

On the Suitability of Discrete-Time Receivers for Software-Defined Radio

Zhiyu Ru; Eric A.M. Klumperink; Bram Nauta

CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such D-T receivers for highly flexible software-defined radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based radio receiver, extra costs are needed to solve these problems.


IEEE Journal of Solid-state Circuits | 2014

Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity

Dlovan H. Mahrof; Eric A.M. Klumperink; Zhiyu Ru; Mark S. Oude Alink; Bram Nauta

High linearity CMOS radio receivers often exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband. Due to nonlinearity and finite gain in the OpAmp, virtual ground is imperfect, inducing distortion currents. This paper proposes a negative conductance concept to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. In- and out-of-band linearity, stability and Noise Figure are also analyzed. The technique is applied to linearize an RF receiver, and a prototype is implemented in 65 nm technology. Measurement results show an increase of in-band IIP 3 from 9 dBm to >20 dBm, and IIP2 from 51 to 61 dBm, at the cost of increasing the noise figure from 6 to 7.5 dB and <;10% power penalty. In 1 MHz bandwidth, a Spurious-Free Dynamic Range of 85 dB is achieved at <;27 mA up to 2 GHz for 1.2 V supply voltage.


IEEE Transactions on Microwave Theory and Techniques | 2013

Using Crosscorrelation to Mitigate Analog/RF Impairments for Integrated Spectrum Analyzers

M.S. Oude Alink; Eric A.M. Klumperink; Andre B.J. Kokkeler; Zhiyu Ru; Wei Cheng; Bram Nauta

An integrated spectrum analyzer is useful for built-in self-test purposes, software-defined radios, or dynamic spectrum access in cognitive radio. The analog/RF performance is impaired by a number of factors, including thermal noise, phase noise, and nonlinearity. In this paper, we present an integrated circuit with two integrated RF-frontends, of which the outputs are crosscorrelated in digital baseband. We show by theory and measurements that the above-mentioned impairments are mitigated by this technique. The presented 65-nm CMOS prototype operates at 1.2 V, and obtains a noise floor below -169 dBm/Hz, an IIP3 of +25 dBm, and more than 20 dB of phase-noise reduction. In a special high-impedance mode, an even lower noise floor below -172 dBm/Hz is obtained.


international symposium on circuits and systems | 2007

Multipath Polyphase Circuits and their Application to RF Transceivers

Eric A.M. Klumperink; Rameswor Shrestha; Eisse Mensink; Gerard J. M. Wienk; Zhiyu Ru; Bram Nauta

Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed.

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