Brent D. Thomas

1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13μm CMOS technology

This paper presents the design and measurement results of a low power high linear digital-to-analog converter in 0.13 mum CMOS. It is powered by a single 1.5 V power supply offering rail-to-rail output capability. The DAC circuit is based on segmented resistor strings to scale the bandgap voltage references. The design of the advanced class-AB amplifier with rail-to-rail input/output for analog output buffering is given in details. Techniques to improve resistor string matching performance to 10-bit resolution are discussed. An effective output de-glitching circuitry is presented. The DAC can operate at 2.0 MSPS with power consumption of 0.5 mW.

A multi-rail shared error ADC with pipeline structure for DC-DC converter digital controller in 0.13µm CMOS technology

This paper presents the design and measurement results of an error ADC with a pipeline structure for DC-DC converter digital controller in 0.13µm technology. The proposed error ADC shared by three voltage rails through an analog MUX. The error signal is amplified by a differential amplifier and a switched capacitor amplifier with a total gain of 10. The amplified error signal is then digitized with a conventional 5b pipeline ADC. The ADC operates at a sampling frequency of 12 MSPS, draws 3mA from a single 1.5V power supply with an area of 500µm by 600µm. Metal fringe capacitors are used for switched-capacitor circuit.

1.5-V 10-Ms/s 8-bit Pipeline ADC in 0.13 μm CMOS using metal fringe capacitor

This paper presents the design and measured results of a 1.5-V 10-Ms/s 8-bit pipeline ADC in 0.13 mum CMOS technology. Since there is no MiM-cap available in this process, a specially designed metal fringe cap was used instead. The ADC can digitalize multi-channel signals through a timing-multiplexing scheme. It has rail-to-rail full scale analog input signal range capability through a rail-to-rail unity-gain buffer and a single- to differential-ended signal transformation stage. It achieves a DNL of +0.46/-0.39 LSB and INL of +0.62/-0.44 LSB with a power dissipation of 3.75 mW from a single 1.5 V power supply and a silicon area of 600 mum times 1000 mum.

A low-voltage high-gain wide-bandwidth class-AB differential difference amplifier

This paper presents a CMOS low-voltage high gain and wide bandwidth differential difference amplifier (DDA). It is based on a robust two-stage class-AB amplifier with cascode Miller compensation. The first stage is a folded-cascode OTA with improved wide swing biasing circuit and the second stage is class-AB output stage biased with translinear circuit. The two input pairs can be either NMOS or PMOS pair. It achieves a DC open loop gain of 80 dB and unity-gain bandwidth of 20 MHz with 380 muA current drawn from a single 1.5 V power supply in 0.13 mum CMOS. Its application for current feedback instrumentation amplifier is discussed.