Hongjiang Song

Automatic antenna tuning unit for software-defined and cognitive radio

In this paper, we propose a new architecture for a closed-loop controlled antenna tuning unit (ATU) system (only transmitting path is shown). In contrast to previous work, no analog-to-digital converters (ADCs) are used. Using the ATU, the narrow instantaneous bandwidth of an electrically small antenna (ESA) is automatically tuned over a much wider frequency range by the ATU. This matching scheme ensures that the narrowband antenna is automatically matched to any desired frequency under all environmental conditions using circuits with practical component values and tolerances. It is imperative that the entire tuning process be completed rapidly using efficient algorithms and fast hardware, and for these algorithms and hardware to consume as little power as possible.

Single chip system for bio-data acquisition, digitization and telemetry

A custom IC has been developed for the acquisition, digitization and telemetry of biological signals in the laboratory. This single chip system consists of a preamplifier, analog to digital converter and frequency shift keyed telemetry. The IC is 2.25 mm/spl times/2.25 mm and consumes 10 mW of power at a power supply voltage of 2.5 V. Data can be transmitted several meters. No off chip components are required except a miniature battery and a straight wire antenna as short as 2 cm. The IC is fabricated in a standard digital CMOS process without a second level of poly-silicon; current mode techniques are used to overcome the lack of linear capacitors.

CMOS potentiostat for chemical sensing applications

We demonstrate a CMOS (complementary metal oxide semiconductor) potentiostat chip fabricated in a standard 0.5 μm CMOS process to perform electrochemical analysis via cyclic voltammetry. This chip contains six independent channels for three electrode systems in electrochemical cells. Our low power circuit has been designed to drive electrochemical reactions in solution using class AB folded cascode amplifiers. The circuit operates with rail to rail input and output and has strong drive ability. We have shown the potentiostat chip is capable of performing cyclic voltammetry (CV) with both potassium ferricyanide and hexaammineruthenium chloride solutions. The chip is capable of differentiating both the composition and concentration of the solution. We compare our results with control experiments on a Gamry commercial electrochemical workstation and demonstrate they are consistent.

CMOS self-powered monolithic light-direction sensor with digitalized output

We present a novel self-powered chip to detect the direction of incident light. This chip directly provides digitized output without the need of any off-chip power supply or optical or mechanical components. The chip was implemented in a standard 0.5 μm CMOS process. A microscale metal baffle was created by stacking all metal layers, contacts, and vias available in the process to produce on-chip shadowing. N-well/p+ photodiode arrays are located on both sides of the baffle to sense light. The photocurrent generated by a photodiode depends on the size of the photodiode and the shadowing. The shadowed area depends on the incident angle of the light. A current mirror circuit is used to compare the currents generated by the photodiodes on the opposite sides of the baffle and, consequently, provide a digital signal to indicate the incident light angle. Compared with the ideal linear digital light-angle detector with the same resolution, the presented sensor achieved the maximum error of only 2 deg over 110 deg test range.

CMOS sensor for sun tracking

We present an optical localization chip capable of detecting the direction of incident light. The chip requires no offchip optical or mechanical components or post-processing (e.g. baffles, slits, mirrors, etc.). The chip was fabricated in a standard 0.5 μm CMOS (complementary metal oxide semiconductor) process. Our approach employs 100 light sensing cells, each having two detectors separated by a metal “wall”. The “wall” was created by stacking all metal layers, contacts and vias available in the process. This metal stack “wall” is used to create on-chip shadowing to facilitate detection. Each optical detection element produces a differential output with the normalized difference between the currents dependent upon the angle of the incident light. The width of the photodiodes is limited by the height of the metal wall to only a few micrometers. To achieve a good sensitivity, 100 cells are placed in parallel. Test results show good sensitivity to the direction and intensity of the incident light with accuracy of 1.9 degrees over a 100 degree range and 1.1 degrees over a 50 degree range.

A General Method to VLSI Polyphase Filter Analysis and Design for Integrated RF Applications

A general approach to the analysis and design of polyphase filters is presented. This method, which is based on the symmetry property and the polyphase signal constraint of the VLSI polyphase filter circuit structures, provides a systematic and significantly simplified path for the analysis and design of various types of VLSI polyphase filters.

CMOS-based on-chip electrochemical sensor

We describe an integrated CMOS electrochemical sensor with on-chip electrodes and packaging. The CMOS chip was fabricated in a standard 0.5 μm CMOS process, and it contains potentiostat circuits with integrated array of three electrode cells. In the potentiostat circuit, we designed high performance folded cascode class-AB operational amplifiers with rail to rail input and output suitable for low power consumption and strong drive capability. The 1.5 mm × 3 mm potentiostat array chip operates from a 5 V supply at 45 μA. A gold electrode array was made on the surface of the CMOS chip using a contact photolithographic process. For compatibility with liquid test environments a packaging approach was developed. The electrochemical sensor with on-chip electrodes was characterized by using cyclic voltammetry (CV) with potassium ferricyanide.

Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing

A novel VLSI SOC signal processing circuit technique based on algorithmic computing architecture, ratio based circuit structures and replica (symmetrical) layout implementation employing basic mixed domain VLSI signal processing circuit elements, across the analog, digital, passive, voltage and current circuit domains, is presented. This approach demonstrated high performance, low power, low layout area penalty and low PVT sensitivity for VLSI SOC signal processing circuit implementations. Design examples are also provided in this paper.

Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication

A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.

A point of care electrochemical impedance spectroscopy device

Electrochemical Impedance Spectroscopy (EIS) is a label-free method of molecular detection of particular interest for biomedical applications. We aim to create a hand-held, easy to use EIS measurement device, for biomolecular detection. Electrochemical cyclic voltammetry systems help millions of diabetics monitor their blood glucose levels 2-8 times per day, but their use is very limited due to the poor lower limit of detection. The EIS technique can be used to detect a much larger array of biomolecules at very low concentration. Our EIS system generates the magnitude and phase of the impedance from test samples via MATLAB, which provides the real and imaginary components of the impedance. The circuit was integrated on a single chip and fabricated in a standard 0.5 μm CMOS technology. A hand-held EIS measurement system was built using the chip and an Arduino Uno to measure a Randles circuit equivalent over the frequency range from 1 Hz to 2 kHz, the measurement and simulation results show excellent agreement.