Bret C. Rothenberg

A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording

A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm/sup 2/ in a 1 /spl mu/m CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm/sup 2/ and dissipates 630 mW.

A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure

A programmable four-tap analog finite-impulse-response filter for use in a decision-feedback equalizer has been realized in a 2-/spl mu/m double-poly CMOS process. It uses a modified transposed structure and double sampling to minimize power dissipation. Also, it uses programmable-gain sample-and-hold amplifiers with a constant feedback factor, input capacitance, and load to reduce the performance variation as a function of programming. The filter is fully differential, occupies an active area of 11.8 mm/sup 2/, and dissipates 56.5 mW.

A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. The DFE cancels intersymbol interference caused by the past 4 decisions. The RAM contents are adapted using digital circuits. In steady-state operation, power dissipation is 260 mW. The active area is 4.5 mm/sup 2/ in a 1-/spl mu/m CMOS process.

A programmable clock generator that uses noise shaping and its application in switched-capacitor filters

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-/spl mu/m CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCFs are reported. >

A 20 Msample/s switched-capacitor finite impulse response filter in 2 /spl mu/m CMOS

Describes a 4-tap transposed FIR filter with a modified structure that uses a combination of 2b and 3b capacitor arrays to implement nearly 5b programmability in each coefficient. It is fully-differential, occupies an active area of 11.8mm/sup 2/ in a 2-/spl mu/m CMOS technology, and dissipates a power of 45mW, about a factor of four less than a comparable direct-form FIR filter.

An 80 Mb/s adaptive DFE detector in 1 /spl mu/m CMOS [hard-disk drives]

This paper describes a continuous-time forward equalizer (CTFE) with one adaptive right-half-plane zero that removes the precursor ISI and an adaptive RAM DFE that removes the postcursor ISI. Because the DFE cancels post-cursor ISI noiselessly, the post-cursor ISI cancellation does not degrade the signal-to-noise ratio. The prototype also includes a 7th-order linear-phase low-pass ladder filter to provide anti-aliasing and to suppress channel noise. The key contribution here is the implementation of this adaptive one-zero forward equalizer in conjunction with the low-pass filter and adaptive mixed-signal RAMDFE on the same IC. Because two continuous-time outputs from the low-pass filter are combined to build the core of the adaptive forward equalizer, it is constructed with little hardware beyond that already required for the low-pass filter.