James E. C. Brown

A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording

A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm/sup 2/ in a 1 /spl mu/m CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm/sup 2/ and dissipates 630 mW.

A mixed-signal decision-feedback equalizer that uses a look-ahead architecture

A mixed-signal decision-feedback equalizer (DFE) that uses a look-ahead architecture is described. The parallelism in the look-ahead DFE (LA DFE) achieves an increase in the data rate over a conventional DFE with a small increase in area. Fully differential analog circuits perform the convolution operation in the LA DFE, and the coefficient adaption is carried out by digital circuits. The LA DFE occupies 23 mm/sup 2/ in a 2-/spl mu/m CMOS process and operates at 50 Mb/s while dissipating 260 mW.

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-/spl mu/m CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-/spl mu/m CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm/sup 2/ and dissipates 165 mW.

A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. The DFE cancels intersymbol interference caused by the past 4 decisions. The RAM contents are adapted using digital circuits. In steady-state operation, power dissipation is 260 mW. The active area is 4.5 mm/sup 2/ in a 1-/spl mu/m CMOS process.

Mixed-mode simulation of a continuous-time Sigma Delta ADC

The use of the C programming language and a commercially available analog and digital (mixed-mode) circuit simulator in the design of a continuous-time multibit sigma-delta ( Sigma Delta ) analog-to-digital converter (ADC) for integration is detailed. The use of the bilinear transformation to generate a discrete-time model of the ADC is shown with an implementation in C. The circuit simulator is introduced and its mixed-mode capabilities are discussed with another implementation of the Sigma Delta ADC. Simulation data is analyzed with the fast Fourier transform (FFT) and compared with actual prototype data. Results indicate a good correlation between simulator and prototype performance.<<ETX>>

Finite impulse response switched-capacitor filters for the delta-sigma modulator D/A interface

Switched-capacitor finite-impulse-response (FIR) low-pass filters that can act as the first stage of the noise filter for a delta-sigma-modulation-based digital-to-analog converter are presented. The output of the filter can be generated at a reduced sampling rate without increasing the noise in the baseband. The lower output sampling rate relaxes the settling requirements of the operational amplifier. The filters have the properties that the coefficients are symmetric and take only integer values. These properties make them especially suitable for MOS switched-capacitor implementation. A symmetric implementation that has low sensitivity to capacitor mismatch is presented. The authors focus on the decimation filter for a second-order delta-sigma modulator, although extension to other order loops is possible. >

A 35 Mb/s mixed-signal decision-feedback equalizer for disk-drive applications

A 5-tap 35 Mb/s mixed-signal adaptive decision feedback equalizer (DFE) has been implemented in a 2-/spl mu/m CMOS technology. The analog circuits are fully differential. Coefficient adaptation is digital, and two adaptation rates are available. The DFE adapts and equalizes at a clock rate of 35 MHz. It occupies 24 mm/sup 2/ and dissipates 165 mW.

A comparison of analog DFE architectures for disk-drive applications

Analog equalizers offer potentially higher speed, lower power and smaller die area than their digital counterparts. Assuming adequate analog forward equalizers are available, we present different integrated circuit (IC) architectures for analog-based decision feedback equalizers, and the strengths and weaknesses of each implementation are discussed.<<ETX>>

Continuous-time forward equalization for the decision-feedback-equalizer-based read channel

A novel adaptive continuous-time forward equalizer (CTFE) for use with a decision-feedback equalizer (DFE) in the magnetic-recording read channel is presented. The forward equalizer is composed of one adaptive zero and can be constructed by adding a weighted version of the read-signal derivative to the read signal itself. The new equalizer is a viable alternative to traditional finite-impulse-response (FIR) forward equalizers in both performance and complexity.

A mixed-signal decision-feedback equalizer that uses parallelism

A mixed-signal decision-feedback equalizer (DFE) that uses parallelism is described. The parallelism in the look-ahead DFE achieves an increase in the data rate over that of a conventional DFE. The DFE occupies 23 mm/sup 2/ in a 2-/spl mu/m CMOS process, operates at 55 Mb/s and dissipates 450 mW.