Stephen H. Lewis

A 10-b 20-Msample/s analog-to-digital converter

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

A digital background calibration technique for time-interleaved analog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.

A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC. With background calibration, peak SNDR is 56.8dB and power dissipation is 234mW from 3.3V. Active area is 12.5mm/sup 2/ in 0.35/spl mu/m CMOS.

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three amplifiers (instead of seven amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a 52 Msamples/s prototype A/D converter that is Intended for a switched digital video application has been implemented in a 0.9-/spl mu/m CMOS technology. The device occupies 15 mm/sup 2/ and dissipates 250 mW from a 5 V supply.

Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation. >

Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter

Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.

A CMOS bandgap reference without resistors

Bandgap references add the forward bias voltage across a pn diode with a voltage that is proportional to absolute temperature (PTAT) to produce an output that is insensitive to changes in temperature. The relative weighting of the voltages added is usually adjusted by trimming the ratio of two resistors. Although inexpensive resistors of suitable values are available in analog CMOS processes, the area of such resistors is increased in standard digital processes because silicide is often used to reduce the sheet resistance of the polysilicon and diffusion layers. As a result, the length and area of the required resistors is increased, increasing not only the cost, but also the susceptibility of the reference operation to substrate noise coupling. One way to overcome this problem is to use an extra mask to selectively block the silicide, but this mask also increases the cost. This paper presents a circuit solution to the above problem: a bandgap reference without resistors. It uses only MOS transistors biased in saturation or cutoff. The devices biased in saturation operate in strong inversion, for which accurate device models are usually available, simplifying the design process, especially in digital CMOS technologies.

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.

A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD

The linearity of analog-to-digital converters (ADCs) is often limited by component mismatches. Trimming can be used to achieve high linearity but cannot track variations over time caused by component aging or by temperature and power-supply changes. Background calibration overcomes this limitation. However, previous background-calibration methods require complicated post processing, occupy some of the range of the analog signal under conversion, or are tailored for a specific type of converter. This ADC uses a queue-based architecture for creating calibration time slots without disturbing the sampling of the input signal. The digital background calibration uses an adaptive algorithm to improve linearity. The queue-based architecture for generating the calibration time slots and the digital-background-calibration method are independent and can be used separately.