Brett Hull

Recent progress in SiC DMOSFETs and JBS diodes at Cree

This paper discusses the recent progress in large area silicon carbide (SiC) DMOSFETs and junction barrier Schottky (JBS) diodes. 1.2 kV and 10 kV SiC DMOSFETs have been produced with die areas greater than 0.64 cm2. SiC JBS diode dies also rated at 1.2 kV and 10 kV have been produced with die areas exceeding 1.5 cm2. These results demonstrate that SiC power devices provide a significant leap forward in performance for industrial electronics applications. At 1.2 kV, SiC DMOSFETs offer a reduction of power loss of greater than 50 % with dies less than half the size when compared to silicon (Si) IGBTs. The SiC JBS diodes offer significant reductions in reverse recovery losses. At 10 kV, there are no Si devices that can compete with SiC on a single device basis. Data on 1.2 kV and 10 kV devices are presented along with future trends.

Influence of oxygen on the activation of p-type GaN

The presence of oxygen in the annealing environment can exhibit a strong influence on the activation of p-GaN, as demonstrated by experiments described in this letter. We activated p-GaN at 600–900 °C in four environments: ultrahigh purity (UHP) N2 gettered to remove residual O2, UHP N2 without gettering, 99.5% UHP N2/0.5% UHP O2, and 90% UHP N2/10% UHP O2. The resistivity of the p-GaN was lowest when O2 was intentionally introduced during activation and was highest when extra care was taken to getter residual O2 from the annealing gas. The experiments also demonstrate that unintentionally incorporated O2 can be at high enough levels to influence the activation process.

Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

High Switching Performance of 1700-V, 50-A SiC Power MOSFET Over Si IGBT/BiMOSFET for Advanced Power Conversion Applications

Due to wider band gap of silicon carbide (SiC) compared to silicon (Si), MOSFET made in SiC has considerably lower drift region resistance, which is a significant resistive component in high-voltage power devices. With low on-state resistance and its inherently low switching loss, SiC MOSFETs can offer much improved efficiency and compact size for the converter compared to those using Si devices. In this paper, we report switching performance of a new 1700-V, 50-A SiC MOSFET designed and developed by Cree, Inc. Hard-switching losses of the SiC MOSFETs with different circuit parameters and operating conditions are measured and compared with the 1700-V Si BiMOSFET and 1700-V Si IGBT, using same test set-up. Based on switching and conduction losses, the operating boundary of output power and switching frequency of these devices are found out in a dc-dc boost converter and compared. The switching dv/dts and di/dts of SiC MOSFET are captured and discussed in the perspective of converter design. To validate the continuous operation, three dc-dc boost converters using these devices, are designed and tested at 10 kW of power with 1 kV of output voltage and 10 kHz of switching frequency. 1700V SiC Schottky diode is used as the blocking diode in each case. Corresponding converter efficiencies are evaluated and the junction temperature of each device is estimated. To demonstrate high switching frequency operation, the SiC MOSFET is switched upto 150 kHz within permissible junction temperature rise. A switch combination of the 1700-V SiC MOSFET and 1700-V SiC Schottky diode connected in series is also evaluated for zero voltage switching turn-ON behavior and compared with those of bipolar Si devices. Results show substantial power loss saving with the use of SiC MOSFET.

Roadmap for megawatt class power switch modules utilizing large area silicon carbide MOSFETs and JBS diodes

Recent dramatic advances in the development of large area Silicon Carbide (SiC) MOSFETs along with their companion JBS diode technology make it possible to design and fabricate high power SiC switch modules. An effort underway by the Air Force Research Laboratory has lead to the development of a 1.2kV/100A SiC dual switch power module capable of operating at a junction temperature of 200°C. Two additional efforts are set on achieving the megawatt goal. An effort by the Army Research Laboratory is focused on 1.2kV modules to be used for traction and power conversion applications. The highest power 1200V all-SiC dual switch power modules produced is capable of 880 amps. A DARPA effort to develop a solid state power substation has produced a 10kV/50A SiC dual switch power module. Higher current modules in both voltage ratings have been designed. These SiC MOSFET modules represent the next level of integration for SiC power devices. This is a critical technical milestone in the progression toward highly reliable, high efficiency, power systems. This technology is relevant in the current energy-conscious environment and will translate to significant energy savings for hybrid and electric vehicles, solar power and alternative energy system inverters, and industrial motor drives.

10 kV, 5A 4H-SiC Power DMOSFET

In this paper, we report 4H-SiC power DMOSFETs capable of blocking 10 kV. The devices were scaled up to 5 A, which is a factor of 25 increase in device area compared to the previously reported value. The devices utilized 100 mum thick n-type epilayers with a doping concentration of 6 times 1014 cm-3 for drift layers, and a floating guard ring based edge termination structure was used. The gate oxide layer was formed by thermal oxidation at 1175 degC, followed by an NO anneal. A peak effective channel mobility of 13 cm2/Vs was extracted from a test MOSFET with a W/L of 150 mum / 150 mum, built adjacent to the power DMOSFETs. A 4H-SiC DMOSFET with an active area of 0.15 cm showed a specific on-resistance of 111 mOmega-cm2 at room temperature with a gate bias of 15 V. The device shows a leakage current of 3.3 muA, which corresponds to a leakage current density of 11 muA-cm-2 at a drain bias of 10 kV

Recent Advances in High-Voltage, High-Frequency Silicon-Carbide Power Devices

The emergence of high-voltage, high-frequency (HV-HF) silicon-carbide (SiC) power devices is expected to revolutionize commercial and military power distribution and conversion systems. The DARPA wide bandgap semiconductor technology (WEST) high power electronics (HPE) program is spearheading the development of HV-HF SiC power semiconductor technology. In this paper, some of the recent advances in development of HV-HF devices by the HPE program are presented and the circuit performance enabled by these devices is discussed

Morphological study of the Al–Ti ohmic contact to p-type SiC

Abstract The composition 70 wt.% Al was recently reported to provide low resistance Al–Ti ohmic contacts with excellent electrical uniformity on p-type SiC. Using scanning electron microscopy and atomic force microscopy, an investigation of the surface morphology and edge definition of the annealed contacts was conducted, and the morphology of the buried metal/semiconductor interface was examined by etching away the contact metallization and imaging the freshly exposed SiC surface. This information provides guidance on the suitability of the contact for devices with small feature sizes and shallow p-type epilayers. Patterned contacts exhibited good edge definition, a root-mean-square surface roughness of 11 nm, and a root-mean-square interfacial roughness of 12 nm. The deepest observed penetration of the metallization into the SiC was 65 nm, and the lateral length scale of the morphological features at the buried metal/semiconductor interface was sufficiently small compared to the active area of the contact to allow good contact-to-contact reproducibility. The interfacial reactions and ohmic contact formation mechanism are considered from the point of view of the materials characterization study presented here and the binary Al–Ti and quaternary Al–C–Si–Ti phase diagrams.

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25degC) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200degC. The diodes show stable operation under continuous forward current injection at 20 A/cm2 and under continuous reverse bias of 8 kV at 125degC. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 A/mus, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25degC-175degC.

Drift-Free, 50 A, 10 kV 4H-SiC PiN Diodes with Improved Device Yields

The path to commericializing a 4H-SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.