Brian A. Worth

SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing

In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.

An SRAM-based FPGA architecture

An SRAM-based FPGA architecture has been developed using a licensed AT6000 architecture base. The logic-cell architecture exploits an efficient, medium-grained, fixed library cell that implements most frequently used synthesis functions. An internal routing structure enables dense designs using a highly connected grid-based routing system and a dedicated I/O routing structure that supports the highest I/O counts available. Dynamic reconfiguration is retained with an underlying SRAM structure like the AT6000.