Steven Paul Hartman

Energyscale for IBM POWER6 microprocessor-based systems

With increasing processor speed and density, denser system packaging, and other technology advances, system power and heat have become important design considerations. The introduction of new technology including denser circuits, improved lithography, and higher clock speeds means that power consumption and heat generation, which are already significant problems with older systems, are significantly greater with IBM POWER6™ processor-based designs, including both standalone servers and those implemented as blades for the IBM BladeCenter® product line. In response, IBM has developed the EnergyScale™ architecture, a system-level power management implementation for POWER6 processor-based machines. The EnergyScale architecture uses the basic power control facilities of the POWER6 chip, together with additional board-level hardware, firmware, and systems software, to provide a complete power and thermal management solution. The EnergyScale architecture is performance aware, taking into account the characteristics of the executing workload to ensure that it meets the goals specified by the user while reducing power consumption. This paper introduces the EnergyScale architecture and describes its implementation in two representative platform designs: an eight-way, rack-mounted machine and a server blade. The primary focus of this paper is on the algorithms and the firmware structure used in the EnergyScale architecture, although it also provides the system design considerations needed to support performance-aware power management. In addition, it describes the extensions and modifications to power management that are necessary to span the range of POWER6 processor-based system designs.

IBM POWER7 systems

This paper describes the system architectures and designs of the IBM POWER7® servers. From the smallest single-processor socket blade to the largest 32-processor-socket 256-core enterprise rack server, each system is designed to fully exploit the performance and the scalability of the POWER7 processor. This paper describes the enhancements made to the memory and input/output subsystems to achieve balanced and scalable designs, the changes made to the power and cooling circuitry to manage energy consumption and power dissipation, and the enhancements made to reliability, availability, and serviceability. These enhancements enable the POWER7 processor-based servers to achieve significant increases in the performance density and the performance per watt, as compared with the predecessor POWER6® processor-based servers.

An SRAM-based FPGA architecture

An SRAM-based FPGA architecture has been developed using a licensed AT6000 architecture base. The logic-cell architecture exploits an efficient, medium-grained, fixed library cell that implements most frequently used synthesis functions. An internal routing structure enables dense designs using a highly connected grid-based routing system and a dedicated I/O routing structure that supports the highest I/O counts available. Dynamic reconfiguration is retained with an underlying SRAM structure like the AT6000.