Brian Mitchell Bass

IBM PowerNP network processor: Hardware, software, and applications

Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates. As a result, more services will have to be performed at the edges, on behalf of both the core and the end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas, in the past, network equipment was based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. This paper provides an overview of the IBM PowerNPTM NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software make it well suited for a wide range of networking applications.

Introduction to the wire-speed processor and architecture

In this paper, we introduce the wire-speed processor (WSP) project, an advanced development project led by IBM Research and the IBM Systems and Technology Group. The WSP represents a generic processor architecture in which processing cores, hardware accelerators, and I/O functions are closely coupled in a system on a chip. The first implementation of the WSP architecture targets applications operating at wire speed (i.e., speeds in which the data are transmitted and processed at the maximum speed allowed by the hardware). These applications include those that involve routers, firewalls, intrusion-prevention systems, and other network analytics. The WSP combines 16 multithreaded IBM PowerPC® cores with special-purpose dedicated accelerators optimized for packet processing, security, pattern matching, compression, Extensible Markup Language (XML) parsing, and I/O for networking that provides four 10-Gb/s bidirectional network links. In this paper, we describe the various system components, the underlying design philosophy involving close integration of these components, and the special system features that were developed to achieve this close integration.

IBM POWER7+ processor on-chip accelerators for cryptography and active memory expansion

With the heightened focus on computer security, IBM POWER® server workloads are spending an increasing number of cycles performing cryptographic functions. Active memory expansion (AME), a technology to dynamically increase the effective memory capacity of a system by compressing and decompressing memory pages, is also enjoying increasing deployment in POWER server systems. Together, cryptography and AME consume enough central processing unit (CPU) cycles in a typical installation to warrant adding dedicated hardware accelerators on the processor chip to offload the compute-intensive parts of these functions from the processor cores. IBM POWER7+™ is the first POWER server to include on-chip hardware accelerators for symmetric (shared key) and asymmetric (public key) cryptography and memory compression/decompression for AME. A true random number generator (RNG) is also integrated on-chip. This paper describes the hardware accelerator framework, including location relative to the cores and memory, accelerator invocation, data movement, and error handling. A description of each type of accelerator follows, including details of supported algorithms and the corresponding hardware data flows. Algorithms supported include the Advanced Encryption Standard, Secure Hash Algorithm, and Message Digest 5 algorithm as bulk cryptographic functions; asymmetric cryptographic functions in support of RSA and elliptic curve cryptography; and a novel dictionary-based compression algorithm with high throughput supporting AME. A presentation of accelerator performance is included.

The IBM power edge of Network™ processor: A wire-speed system-on-a-chip with 16 Power™ cores / 64 threads and optimized HW acceleration

Presents a collection of slides covering the following topics: Network processor; IBM power edge; wire-speed system-on-a-chip; interconnect architecture; PowerPC processing element architecture; DDR3 DRAM controller; accelerator architecture; accelerator interface; compression/decompression; crypto data mover; XML engines; packet processor architecture; and PCI-Express.