Santosh P. Gaur

Improved performance of IBM Enterprise System/9000 bipolar logic chips

The performance required for logic gate arrays by the IBM Enterprise System/9000TM (ES/9000TM) family of water-cooled processors was obtained by redesigning chips that previously consisted of emitter-coupled logic (ECL) circuits. Multiple bipolar logic circuit families were implemented for the first time on a single IBM chip by using a modular cell approach. In 60% of the ECL circuits, ac coupling in ECL gates reduced the maximum operating power per ECL circuit on ES/9000 chips by S0% and decreased the signal delay per loaded gate by 30%, to 150 ps. About 10-20% of the remaining ECL circuits were replaced by differential current switches (DCS) which dissipated less power and improved the overall chip performance. Circuits to communicate between ECL and DCS circuit families and to improve DCS circuit reliability were included on the ES/9000 chips without affecting logic function density. Introduction Recent advances in bipolar logic semiconductor processing have increased circuit densities on a cliip by an order of magnitude [1, 2]. However, packaging improvements have only doubled the quantity of heat that can be removed from a chip [3]. Consequently, a 50% reduction in the average operating power per logic circuit is required. Bipolar chips in IBM 3090TM processors are composed of ECL circuits which operate at high (15 mW/single phase) power and dissipate significant quantities of heat. In ES/9000 chips, a decrease in power per circuit increases the delays due to the load associated with the capacitance of interconnecting wires. The interconnections introduce a measure of circuit loading which doubles the sensitivity of a circuits performance to fan-out and wire lengths. Vertical geometry device design improvements reduce delays with intrinsic, but not extrinsic, loads. Advanced metallurgies do not compensate for the high wiring capacitance that arises from the longer wire lengths due to a doubling of the ES/9000 chip areas. The performance of gate arrays required by the ES/9000 family of mainframe

Verification of heavy doping parameters in semiconductor device modeling

A mathematical model has been formulated which solves semiconductor transport equations with heavy-doping corrections. This model requires only the device dimension and doping profile as input parameters. Model predictions agree very well with measured terminal characteristics of various NPN and PNP transistor structures and support heavy-doping parameters used in the model.

High performance packaged electronics for the IBM ES9000 mainframe

An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.<<ETX>>

Simplifying SoC design with the customizable control processor platform

We describe the customizable control processor (CCP) platform based on PowerPC/spl reg/ 440 processor with a target frequency of 533 MHz as well as its design methodology. The hardened region of the chip contains cores and features found in many control and communications applications. The custom area of the chip allows for each application of CCP to be personalized with cores from the IBM core library or with unique logic implemented in IBM ASIC standard cell. A predefined logic template (customer logic file) with a set of standard CoreConnect/spl reg/ ports can be personalized with any function that can be implemented in the IBM ASIC technology. The customer logic file is synthesized placed and wired in the custom area of the chip. The custom area of the chip could be configured with approximately 2 M gates of logic. With all mask levels being personalized other configurations could include SRAM, and embedded DRAM incorporated in the custom logic. There are around 263 pre-assigned I/O for the hardened portion of the chip as well as around 177 I/O sockets available in the custom region to personalize. The CCP provides a flexible platform and design environment that effectively reduces the design effort, design time, and the design cost of systems on chip.

Analysis of high-voltage switching transistors by a two-dimensional mathematical model

A two-dimensional mathematical model which includes the avalanche multiplication and internal self-heating effects has been used to predict the internal behavior of a typical high-voltage power transistor design. Collector n--n+interface is the region of high electrical and thermal stresses which cause second breakdown failure at high-current and high-voltage operating conditions.