Brian W. Messenger

Reliability investigation of NiPtSi electrical fuse with different programming mechanisms

The reliability of NiPtSi/p-poly Si electrical fuses with different programming mechanisms, i.e., electromigration and thermal rupture, was investigated in terms of fuse resistance stability and fuse array functionality for the 65-nm technology node. The resistance of the fuses programmed within the electromigration programming window was found to be very stable; resistance shift was only observed on fuses programmed in the underprogrammed mode, which results in incomplete electromigration. For fuses programmed with the thermal rupture mechanism, both resistance shift and functional sensing fails were observed. Furthermore, a guard band was defined for fuses programmed with an electromigration mechanism to ensure sufficient margins for fuse reliability. However, a guard band cannot be defined for fuses programmed with a rupture mode due to the unpredictable nature of the rupture programming mechanism. The unprogrammed fuse elements were shown to be stable through extensive reliability evaluations.

Early detection of electrical defects in deep trench capacitors using voltage contrast inspection

Improvement of learning cycle time and mean time to detect issues is integral to keeping up with the increasing pace needed in semiconductor technology development. Use of electron beam voltage contrast inspection as an early assessment of electrical defectivity of embedded dynamic random access memory in IBMs deep trench capacitor technology allows for detection of all major initial processing electrical defects months before conventional techniques. Product-like and specially designed on chip diagnostic structures are inspected as soon as active layer patterning and isolation is complete. This enables much earlier identification of electrical defectivity. Examples discussed include electrically open single connections, electrical short circuits to neighboring cells in an array, and cells that have short circuits to the silicon substrate. Physical failure analysis and correlation to other in-line measurement and electrical test signals were performed to verify the voltage contrast inspection results. Robust and reliable results enable regular use of this technique to assess electrical health of critical structures early in the process sequence on and to facilitate increased yield improvement learning cycles beyond what is otherwise possible.

Methodology for trench capacitor etch optimization using voltage contrast inspection and special processing

Embedded DRAM will play a much larger part in IBM server microprocessors for new SOI technologies. Etch of a deep trench (DT) into the substrate, which is used to form the capacitor, is a complicated multi-step process. One of the key elements is etch of the buried oxide layer. Voltage contrast (VC) inspection is used to detect defective DTs and can differentiate between opens in the buried oxide and those in the oxide hard mask. So these defects have a VC signal, special processing is needed to seal off the SOI layer. The process of finding the right beam conditions to detect the opens in the buried oxide, which are very subtle, is described. Failure analysis of these defects is also presented.