Chengwen Pei

A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications

We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real estate to fabricate the same capacitance as standard planar gate oxide capacitors. Additionally, the trench decap demonstrates a dramatic improvement in leakage compared to standard planar gate oxide capacitors - as much as 105 improvement in leakage can be realized using trench decaps instead of conventional planar decap designs.