Brian Young

On-chip inductance modeling and analysis

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices.

Model and analysis for combined package and on-chip power grid simulation

We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power distribution grids. These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a statistical switching current model for the switching devices. Moreover, three new simulation techniques are presented for problem size-reduction and speed-up. Results of application of these techniques on three PowerPC/sup TM/ microprocessors are also presented.

Measurement of package inductance and capacitance matrices

A technique is presented for the measurement of resistance, inductance, conductance, and capacitance matrices of large pin count electronic packages. Circuit analysis of an assumed lumped model is used to define a measurement technique based on two sets of measurements on specially prepared samples. Formulas are derived for use with network analyzer measurements. Measurements and simulations on a 208-lead quad flat pack show that the method attains good accuracy for all but the small values of the conductance matrix.

Return path inductance in measurements of package inductance matrixes

Circuit theory is applied to derive a transformation to move the reference in a partial inductance matrix from one lead to another. A package is experimentally characterized with three very different return paths to produce radically different partial inductance matrixes. These matrixes are re-normalized and shown to be equal except for the initial measurement return path. Additional measurements show that repeatability is not affected by the choice of measurement return path. Bandwidth can be affected by the measurement return path.

Return path inductance in measurements of package inductance matrices

Circuit theory is applied to show that the effects of the return path on measured inductance matrices can be negligible. Measured inductance matrices using three distinctly different return paths are shown to be very different but equivalent.

Enhanced LVDS for signaling on the RapidIO/sup TM/ interconnect architecture

Low voltage differential signaling (LVDS) is an established signaling standard for data rates up to about 600 Mb/s. The RapidIO interconnect architecture is an emerging protocol that uses LVDS for unidirectional point-to-point communication between two components on a board or in a backplane environment. The simulated performance and design trade-offs of source-terminated LVDS are shown for enhanced data rates of over 2 Gb/s.

A custom package autoprober

To enable the characterization of packages for their complete N/spl times/N inductance and capacitance matrices, a custom package autoprober was designed, constructed, and programmed. Several essential features are implemented to enable 24 hour lights-out operation, including automatic calibration, adaptive probing, data checking, and e-mail notification.

Figures-of-merit for package electrical roadmaps

Transient currents created by on-chip switching in cores and by off-chip drivers cause noise to be generated on package parasitics. Simple mathematical models for the noise are used to derive figures-of-merit for the two cases of on-chip and off-chip switching. SIA Roadmap packaging trends are used with the figures-of-merit to produce package noise trends.