Rajat Chaudhry

Cell processor low-power design methodology

Power consumption is a major challenge in VLSI design. Power-constrained designs must attack power reduction with many techniques and require tools to accurately predict the power consumption. These tools give designers feedback on the efficiency of the power management logic. We present the basic methodology behind cycle-accurate power estimation. This forms a basis for explaining the techniques used to reduce power in the first-generation Cell processor, along with data that correlates our hardware measurements against power estimates.

A cycle accurate power estimation tool

Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designers on the efficiency of the power management logic. In this paper we present the methodology behind a cycle accurate power estimation tool. This tool was used to estimate the power of a first generation CELL Processor. The tool extracts switching and clock activity from RTL simulations and applies them to transistor level macro power models to calculate the power for every cycle of the simulation trace