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Dive into the research topics where Rajendran Panda is active.

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Featured researches published by Rajendran Panda.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2002

Hierarchical analysis of power distribution networks

Min Zhao; Rajendran Panda; Sachin S. Sapatnekar; David T. Blaauw

Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of todays designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.


design automation conference | 1998

Design and analysis of power distribution networks in PowerPC/sup TM/ microprocessors

Abhijit Dharchoudhury; Rajendran Panda; David T. Blaauw; Ravi Vaidyanathan; Bogdan Tutuianu; David R. Bearden

We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC™ 750 microprocessor is presented.


asia and south pacific design automation conference | 2003

Statistical delay computation considering spatial correlations

Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Min Zhao; Kaushik Gala; Rajendran Panda

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.


design automation conference | 2000

On-chip inductance modeling and analysis

Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Brian Young; Junfeng Wang; David T. Blaauw

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices.


international symposium on low power electronics and design | 2000

Model and analysis for combined package and on-chip power grid simulation

Rajendran Panda; David T. Blaauw; Rajat Chaudhry; Vladimir Zolotov; Brian Young; Ravi Ramaraju

We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power distribution grids. These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a statistical switching current model for the switching devices. Moreover, three new simulation techniques are presented for problem size-reduction and speed-up. Results of application of these techniques on three PowerPC/sup TM/ microprocessors are also presented.


international conference on computer aided design | 2003

Vectorless Analysis of Supply Noise Induced Delay Variation

Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda

The impact of power supply integrity on a design has become acritical issue, not only for functional verification, but also for performanceverification. Traditional analysis has typically applied a worstcase voltage drop at all points along a circuit path which leads to avery conservative analysis. We also show that in certain cases, thetraditional analysis can be optimistic, since it ignores the possibilityof voltage shifts between driver and receiver gates. In this paper, wepropose a new analysis approach for computing the maximum pathdelay under power supply fluctuations. Our analysis is based on theuse of superposition, both spatially across different circuit blocks,and temporally in time. We first present an accurate model of pathdelay variations under supply drops, considering both the effect oflocal supply reduction at individual gates and voltage shifts betweendriver/receiver pairs. We then formulate the path delay maximizationproblem as a constrained linear optimization problem, consideringthe effect of both IR drop and LdI/dt drops. We show how correlationsbetween currents of different circuit blocks can be incorporatedin this formulation using linear constraints. The proposed methodswere implemented and tested on benchmark circuits, including anindustrial power supply grid and we demonstrate a significantimprovement in the worst-case path delay increase.


design, automation, and test in europe | 2005

Stochastic Power Grid Analysis Considering Process Variations

Praveen Ghanta; Sarma B. K. Vrudhula; Rajendran Panda; Janet Meiling Wang

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grids electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis.


international conference on computer aided design | 2002

Noise propagation and failure criteria for VLSI designs

Vladimir Zolotov; David T. Blaauw; Supamas Sirichotiyakul; Murat R. Becer; Chanhee Oh; Rajendran Panda; Amir Grinshpon; Rafi Levy

Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. After the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. This is the second issue that we discuss in this paper. Traditionally, noise failure criteria have been based on unity gain points of the DC or AC transfer curves. However, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. In this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. The proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits.


design automation conference | 2004

A stochastic approach to power grid analysis

Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda

Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation infor-mation between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current wave-forms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.


international conference on computer aided design | 1997

Library-less synthesis for static CMOS combinational logic circuits

Sergey Gavrilov; Alexey Glebov; Satyamurthy Pullela; Stephen C. Moore; Abhijit Dharchoudhury; Rajendran Panda; Gopalakrishnan Vijayan; David T. Blaauw

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.

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