Brook Chao

Electromigration enhanced intermetallic growth and void formation in Pb-free solder joints

A kinetic analysis was formulated for electromigration enhanced intermetallic evolution of a Cu–Sn diffusion couple in the Sn-based Pb-free solder joints with Cu under bump metallurgy. The simulated diffusion couple comprised the two terminal phases, Cu and Sn, as well as the two intermetallic phases, Cu3Sn and Cu6Sn5, formed between them. The diffusion and electromigration parameters were obtained by solving the inverse problem of the electromigration enhanced intermetallic growth, and they were compatible with the literature values. Finite difference method was applied to the whole simulated domain to solve for the mass transport kinetics within the intermetallic phases and across each interface of interest. Simulation showed that, when electromigration effect was absent (zero current), intermetallic growth followed a parabolic law, suggesting a diffusion controlled mechanism for thermal aging. However, under significant current stressing (4×104A∕cm2), the growth of the dominant intermetallic Cu6Sn5 cle...

Effect of contact metallization on electromigration reliability of Pb-free solder joints

The effect of underbump metallization (UBM) on electromigration (EM) lifetime and failure mechanism has been investigated for Pb-free solder bumps of 97Sn3Ag composition in the temperature range of 110–155°C. The EM lifetime of the SnAg Pb-free solders with either Cu or Ni UBM was found to be better than the eutectic SnPb (63Sn37Pb) solders but worse than high-Pb (95Pb5Sn) solders. In the test temperature range, the EM lifetimes were found to be comparable for Cu and Ni UBMs but with different activation energies: 0.64–0.72eV for Cu UBM and 1.03–1.11eV for Ni UBM. EM failure was observed only in solder bumps with electron current flow from UBM to the substrate. Failure analysis revealed that EM damage was initiated by the formation of intermetallic compounds (IMC) at the UBM∕solder interface which was found to be significantly enhanced by mass transport driven by the electron current. Under EM, the continued growth of IMC with the dissolution of the UBM and the accumulation of Kirkendall voids resulted in...

Recent advances on kinetic analysis of electromigration enhanced intermetallic growth and damage formation in Pb-free solder joints

A comprehensive kinetic analysis was established to investigate the electromigration (EM) enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints with Cu under bump metallization (UBM). The kinetic model takes into account Cu–Sn interdiffusion and current stressing. Derivation of the diffusion coefficients and the effective charge numbers for the intermetallic compounds is an essential but challenging task for the study of this multi-phase multi-component intermetallic system. A new approach was developed to simultaneously derive atomic diffusivities and effective charge numbers based on simulated annealing (SA) in conjunction with the kinetic model. A consistent set of parameters were obtained, which provided important insight into the diffusion behaviors driving the IMC growth. The parameters were used in a finite difference model to numerically solve the IMC growth problem and the result accurately correlated with the experiment. EM reliability test revealed that the ultimate failure of the solder joints was caused by extensive void formation and subsequent crack propagation at the intermetallic interface. This damage formation mechanism was analyzed by first considering vacancy transport under current stressing. This was followed by a finite element analysis on the crack driving force induced by void formation. This paper is concluded with a future perspective on applying the kinetic analysis and damage mechanism developed to investigate the structural reliability of the through-Si-via in 3D interconnects.

Multi-level Step and Flash Imprint Lithography for Direct Patterning of Dielectrics

The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.

Simulation and design of planarizing materials for reverse-tone step and flash imprint lithography

Reverse-tone step and flash imprint lithography SFIL-R shows promise as a cost-efficient, high-resolution patterning technique; however, the generation of satisfactory patterns requires the successful application of a planarizing topcoat over topography through spincoating. Photopolymerizable nonvolatile fluids are ideal topcoat materials because they planarize better than volatile fluids during spincoating and can continue to level after spincoating. Fluid mechanics analyses indicate that complete planarization using capillary force is slow. Therefore, defining the acceptable or critical degree of planarization DOPcrit becomes necessary. Finite difference simulation of the spincoat and postspin leveling processes was used to determine the planarization time for various topographic and material property combinations. A new material, Si-14, was designed to have ideal planarization characteristics low viscosity-15.1 cP; low shrinkage-5.1% and satisfy SFIL-R processing requirements oxygen etch resistance-33 wt% silicon, photocurable and was used to validate our models through profilometry and interferometry experiments. During spincoating, minimizing the spin speed generates more planar films; however, this increases the spin time. To rectify this problem, a two-stage spincoating process-a first step with high spin speeds to achieve the target thickness quickly and a second step with low spin speeds to improve planarization-was proposed and experimentally demonstrated.

A study of electromigration failure in Pb-free solder joints

Electromigration (EM) lifetime and failure mechanisms have been investigated for SnAg Pb-free solder bumps with two types of under bump metallurgy (UBM). The activation energy was determined to be 0.64/spl sim/0.72 eV for Pb-free solders with Cu UBM and 1.03/spl sim/1.11 eV with Ni UBM. EM failure was observed only in solder bumps with electron current flow from UBM to the substrate. SEM and EDX analysis revealed a failure mechanism for solder bumps with Ni UBM caused by the dissolution of UBM as a result of Ni migration and subsequent solder cracking or de-wetting. The failure mechanism of Cu UBM samples showed temperature dependence. At higher temperatures, Cu UBM dissolved continuously while at lower temperatures, open failure was caused by crack formation at the Cu/sub 3/Sn/Cu/sub 6/Sn/sub 5/ interface with little damage to the UBM. This is attributed to a difference of Cu diffusivity in Cu/sub 3/Sn and Cu/sub 6/Sn/sub 5/. The EM lifetime of Pb-free solder was found to be much better than eutectic solders but worse than high-Pb solders at the same temperature.

Dual damascene BEOL processing using multilevel step and flash imprint lithography

Step and Flash Imprint Lithography (S-FIL®) in conjunction with Sacrificial Imprint Materials (SIM) shows promise as a cost effective solution to patterning sub 45nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a high throughput and low cost BEOL process. This paper describes the integration of S-FIL into an industry standard Cu/low-k dual damascene process that is being practiced in the ATDF at Sematech in Austin. The pattern transferring reactive ion etching (RIE) process is the most critical step and was extensively explored in this study. In addition to successful process development, the results provide useful insight into the optimal design of multilevel templates which must take into account the characteristics of both the imaging material and the dielectric layer. The template used in this study incorporates both the via and trench levels of an M2 (Metal 2) test vehicle that incorporates via chains with varying via dimensions, Kelvin test structures, serpentines, etc. The smallest vias on the template are 120nm vias with an aspect ratio of 2.0 and the smallest dense lines are 125nm/175nm with an aspect ratio of 2.9. Two inter-level dielectrics (ILD), Coral® and Black Diamond® were studied. No trench etch stop was incorporated in the ILD film stack. A multi-step, in-situ etching scheme was developed that achieves faithful pattern transfer from the sacrificial imprint material (SIM) into the underlying low k ILD with surprisingly wide process latitude. This multi-step scheme includes the following etch steps: a residual layer open, a via etch, a trench descum, a trench etch, and an SIM removal ash. Among these steps, the trench etch was found to be the most challenging to develop and it holds the key to producing high aspect ratio dual damascene features. An etching chemistry based on two fluorocarbon gases, CF4 and C4F8, was found to be very effective in delivering the desired etch profiles with optimal sidewall angle, minimal facet formation. The optimized etch process can be exploited to provide substantial size reduction and/or increased aspect ratio relative to the template. In this way structures with final critical dimensions of 95nm in vias with aspect ratio of 3.0 and 67nm/233nm in dense lines with aspect ratio of 3.6 were demonstrated with wide process latitude. This enables manufacturing of the template at larger dimensions, which simplifies both fabrication and inspection. The successful development of the dual damascene RIE process at the second metal (M2) level was demonstrated in a mixed and matched build with an ATDF standard first layer metal (M1) process. The M1 dielectric was TEOS and was patterned by 248nm lithography. The M2 and Via levels used Coral as ILD and both levels were patterned simultaneously by S-FIL using Molecular Imprint Imprio 55 and Imprio 100 imprint tools. This electrical test vehicle provided solid evidence that S-FIL is fully compatible with industry standard dual damascene process.

Investigation of Intermetallic Compound Growth Enhanced by Electromigration in Pb-Free Solder Joints

An efficient numerical method based on simulated annealing was developed to extract the diffusion and electromigration (EM) parameters for multi-phase intermetallic compounds (IMCs) formed between under-bump-metallurgy (UBM) and solder bumps. This method was applied to the growth of Cu-Sn IMCs during thermal aging and electromigration in Pb-free solder joints with Cu UBM. Diffusion coefficients and effective charge numbers of Cu and Sn in IMCs were derived in this study. The simulated annealing approach provided superior efficiency and accuracy over the conventional grid heuristics, and was proven to be particularly useful for analyzing multiple parameters in multiphase systems, such as solder joints. The effect of EM-enhanced IMC growth on stress fields in solder joints was also studied using finite element analysis. The negative volumetric strain appeared to be an important factor contributing to the degradation of EM reliability of solder joints.

Moisture Transport and its Effects on Fracture Strength and Dielectric Constant of Underfill Materials

With continuing demands on increasing die size and device density, underfills are widely used in flip-chip and ball-grid array packages for improvement of reliability. Fracture of the underfill/die interfaces is often observed, particularly at the die corners under a humid environment, raising serious reliability concerns. Moisture uptake can also increase the dielectric constant of underfill materials to degrade the electrical performance of the packages. In this paper, we investigated the diffusion kinetics of moisture and its effects on the fracture energy and effective dielectric constant for two underfill materials. The moisture transport kinetics was studied by a TGA weight loss method and a capacitance measurement method. Based on these results together with diffusion modeling, Arrhenius type relations for moisture diffusion constant and moisture concentration ratio were determined. The interfacial fracture energy of underfills sandwiched by SiN-deposited Si-substrate was measured under various humidity conditions using a double cantilever beam (DCB) method. The crack driving force was systematically reduced by more than 40% as the moisture content increased to saturation in the samples. The locus of failure was cohesive inside underfill materials. Sample preparation technique comprising narrower underfill layer than Si-substrate reduced the incidents of premature failure during testing. Finally, the moisture effect on the increase of dielectric constant was determined using capacitance measurement methods. The dielectric relaxation factor per unit moisture content is reported for the two underfills.

High resolution nanoimprint templates for dual damascene: fabrication and imprint results

A dual damascene template fabrication process has been developed, which enables the structuring of high-resolution, high-aspect pillars on top of lines. Based on this technology templates with three different designs have been fabricated and characterized. Two templates are dedicated for an assessment of the fabrication process using a regular test design on one hand and an arbitrary CMOS design on the other hand. With the third template via chains shall be later realized as demonstrator for electrical tests. The templates have been imprinted in resist and sacrificial material on an Imprio 55 and an Imprio 100 tool. The usability of each fabricated template could be confirmed for the specific application. For the template manufacturing a Vistec variable shape e-beam (VSB) writer SB352HR and appropriate positive-tone and negative-tone chemically amplified resists (CAR) have been used.