Frank Palmieri

Implementation of an imprint damascene process for interconnect fabrication

Advanced integrated circuits require eight or more levels of wiring to transmit electrical signal and power among devices and to external circuitry. Each wiring level connects to the levels above and below it through via layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around 20 process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. Through use of a template with two tiers of patterning, a single imprint lithography step can replace two photolithography steps. Further improvements in efficiency are possible if the imprint material is itself a functi...

Direct Imprinting of Dielectric Materials for Dual Damascene Processing

Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.

Design of Reversible Cross-Linkers for Step and Flash Imprint Lithography Imprint Resists

Progress in the semiconductor manufacturing industry depends upon continuous improvements in the resolution of lithographic patterning through innovative materials development and frequent retooling with expensive optics and radiation sources. Step and Flash Imprint Lithography is a low-cost, nanoimprint lithography process that generates nanopatterned polymeric films via the photopolymerization of low-viscosity solutions containing cross-linking monomers in a transparent template (mold). The highly cross-linked imprint materials are completely insoluble in all inert solvents, which poses a problem for reworking wafers with faulty imprints and cleaning templates contaminated with cured imprint resist. Degradable cross-linkers provide a means of stripping cross-linked polymer networks. The controlled degradation of polymers containing acetal- and tertiary ester-based cross-linkers is demonstrated herein. The viscosity and dose to cure are presented for several prepolymer formulations, along with imprint resolution and tensile modulus results for the cured polymers. Optimum conditions for de-cross-linking and stripping of the cross-linked polymers are presented, including demonstrations of their utility.

Feature filling modeling for step and flash imprint lithography

The authors analyze the feature filling phenomena for step and flash imprint lithography (SFIL) via diffusion of a gas, entrapped in the features, through liquid imprint resist. The model and simulation for the dynamics of feature filling including gas dissolution during the SFIL imprint step is presented. Several factors including the gas concentration profile across the liquid resist drop, the filling progression, and the total filling time for different pattern configurations are investigated to quantify feature filling. Simulation results show that initial filling is pressure controlled and very rapid [∼O(1ms)]. The rest of the feature filling is diffusion controlled, but fast enough [∼O(1s)] to conclude that diffusion of entrapped gas is not a cause for nonfilling of features. Also, the result that the smaller size features fill faster than the larger ones (with the same depth) makes SFIL the prime contender for high resolution and high throughput next generation lithography.

Vinyl ether formulations for step and flash imprint lithography

Acrylates have been used as patterning monomers in step and flash imprint lithography. Vinyl ether formulations have a lower viscosity, faster curing rate, and higher tensile strength than acrylate formulations. However, the lack of commercially available, silicon-containing vinyl ether monomers has required the synthesis of several new vinyl ethers. An ideal monomer has low viscosity and low vapor pressure. The vapor pressure of silicon-containing vinyl ethers was predicted using the Joback-Reid, Lyderson, and Lee-Kesler methods. BVMDSO (1,1,3,3-tetramethyl-1,3-bis(vinyloxymethyl)-disiloxane) has the lowest viscosity of the synthesized silicon-containing vinyl ethers that meet the volatility requirement for a 80 pl dispense volume. The formulation of BVMDSO, CHDVE (cyclohexanedimethanol divinyl ether), and TEGDVE (triethylene glycol divinyl ether) shows good tensile strength and modulus. The formulation of BVMDSO, CHDVE, TEGDVE, and fluorinated acetate can print a 30 nm line because it has a low separati...

Multi-level Step and Flash Imprint Lithography for Direct Patterning of Dielectrics

The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.

Laser ablative surface treatment for enhanced bonding of Ti-6Al-4V alloy.

Adhesive bonding offers many advantages over mechanical fastening, but requires certification before it can be incorporated in primary structures for commercial aviation without disbond-arrestment features or redundant load paths. Surface preparation is widely recognized as the key step to producing robust and predictable adhesive bonds. Surface preparation by laser ablation provides an alternative to the expensive, hazardous, polluting, and less precise practices used currently such as chemical-dip, manual abrasion and grit blast. This report documents preliminary testing of a surface preparation technique using laser ablation as a replacement for the chemical etch and abrasive processes currently applied to Ti-6Al-4V alloy adherends. Surface roughness and surface chemical composition were characterized using interference microscopy and X-ray photoelectron spectroscopy, respectively. A technique for fluorescence visualization was developed which allowed for quantitative failure mode analysis. Wedge crack extension testing in a hot, humid environment indicated the relative effectiveness of various surface treatments. Increasing ablation duty cycle reduced crack propagation and adhesive failure. Single lap shear testing showed an increase in strength and durability as laser ablation duty cycle and power were increased. Chemical analyses showed trends for surface chemical species, which correlated with improved bond strength and durability.

Dual damascene BEOL processing using multilevel step and flash imprint lithography

Step and Flash Imprint Lithography (S-FIL®) in conjunction with Sacrificial Imprint Materials (SIM) shows promise as a cost effective solution to patterning sub 45nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a high throughput and low cost BEOL process. This paper describes the integration of S-FIL into an industry standard Cu/low-k dual damascene process that is being practiced in the ATDF at Sematech in Austin. The pattern transferring reactive ion etching (RIE) process is the most critical step and was extensively explored in this study. In addition to successful process development, the results provide useful insight into the optimal design of multilevel templates which must take into account the characteristics of both the imaging material and the dielectric layer. The template used in this study incorporates both the via and trench levels of an M2 (Metal 2) test vehicle that incorporates via chains with varying via dimensions, Kelvin test structures, serpentines, etc. The smallest vias on the template are 120nm vias with an aspect ratio of 2.0 and the smallest dense lines are 125nm/175nm with an aspect ratio of 2.9. Two inter-level dielectrics (ILD), Coral® and Black Diamond® were studied. No trench etch stop was incorporated in the ILD film stack. A multi-step, in-situ etching scheme was developed that achieves faithful pattern transfer from the sacrificial imprint material (SIM) into the underlying low k ILD with surprisingly wide process latitude. This multi-step scheme includes the following etch steps: a residual layer open, a via etch, a trench descum, a trench etch, and an SIM removal ash. Among these steps, the trench etch was found to be the most challenging to develop and it holds the key to producing high aspect ratio dual damascene features. An etching chemistry based on two fluorocarbon gases, CF4 and C4F8, was found to be very effective in delivering the desired etch profiles with optimal sidewall angle, minimal facet formation. The optimized etch process can be exploited to provide substantial size reduction and/or increased aspect ratio relative to the template. In this way structures with final critical dimensions of 95nm in vias with aspect ratio of 3.0 and 67nm/233nm in dense lines with aspect ratio of 3.6 were demonstrated with wide process latitude. This enables manufacturing of the template at larger dimensions, which simplifies both fabrication and inspection. The successful development of the dual damascene RIE process at the second metal (M2) level was demonstrated in a mixed and matched build with an ATDF standard first layer metal (M1) process. The M1 dielectric was TEOS and was patterned by 248nm lithography. The M2 and Via levels used Coral as ILD and both levels were patterned simultaneously by S-FIL using Molecular Imprint Imprio 55 and Imprio 100 imprint tools. This electrical test vehicle provided solid evidence that S-FIL is fully compatible with industry standard dual damascene process.

Photocurable silicon-based materials for imprinting lithography

Step and flash imprint lithography (SFIL) is low cost, high resolution patterning process and has found its way into a multitude of front end of the line (FEOL) and back end of the line (BEOL) applications. SFIL-R, a reverse tone variant of SFIL, and imprintable dielectrics are examples of such applications, and both require the design of specialized, silicon-based materials. Polyhedral oligomeric silsesquioxane (POSS) liquids were modified through a dual functionalization strategy to introduce photosensitive acrylate and thermally curable benzocyclobutane (BCB) groups to the molecule. The optimal functional group ratio was observed to be 3:5 acrylate to BCB, and the result was an imprintable dielectric with good mechanical properties and minimal post-exposure shrinkage. Thermal gravimetric analysis (TGA) revealed good thermal stability with minimal mass loss under annealing conditions of 400°C for 2 hours. Si-14 was designed to be a non-volatile, etch-resistant planarization layer for SFIL-R application. A polydimethylsiloxane (PDMS) derivative was modified to introduce acrylate functional groups and side branching for photosensitivity and low viscosity, respectively. Characterization of the material showed ideal planarization characteristics - low volatility (0.77 Torr at 25°C), low viscosity (15.1 cP), and minimal post-exposure shrinkage (5.1%).

Planarization for reverse-tone step and flash imprint lithography

Understanding the dynamics of thin film planarization over topography is a key issue in the reverse-tone step and flash imprint lithography (SFIL-R) process. Complete planarization of a film over large, isolated topography poses an enormous challenge, since the driving force for planarization, the capillary pressure, continuously weakens as the film becomes more planar. For SFIL-R, only a specific degree of planarization (DOP) needs to be achieved before pattern transfer is possible. This paper presents the derivation of an inequality statement describing the required extent of planarization for successful pattern transfer. To observe how this critical DOP value (DOPcrit), and its corresponding leveling time (Tcrit) vary with materials and topographic properties, finite difference simulation was utilized to model planarization of a thin film over isolated topography after the spincoating process. This model was verified experimentally for various film thickness to substrate height ratios using interferometry to monitor silicon oil planarization over isolated trenches and lines. Material and topographic parameters were shown to not have a dramatic impact on DOPcrit; however, the critical leveling time increased considerably at DOPcrit values above 60 percent.