Vincent C. Gaudet

Stochastic iterative decoders

This paper presents a stochastic algorithm for iterative error control decoding. We show that the stochastic decoding algorithm is an approximation of the sum-product algorithm. When the codes factor graph is a tree, as with trellises, the algorithm approaches maximum a-posteriori decoding. We also demonstrate a stochastic approximations to the alternative update rule successive relaxation. Stochastic decoders have very simple digital implementations which have almost no RAM requirements. We present example stochastic decoders for a trellis-based Hamming code, and for a block turbo code constructed from Hamming codes

Low-voltage CMOS circuits for analog iterative decoders

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented.

On multiple slice turbo codes

The main problem with the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem by using a new family of turbo codes called Multiple Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a constrained interleaver structure that allows the parallel decoding of the P independent codewords in each dimension. The optimization of the interleaver is described. A high degree of parallelism is obtained with equivalent or better performance than thedvb-rcs turbo code. For very high throughput applications, the parallel architecture decreases both decoding latency and hardware complexity compared to the classical serial architecture, which requires memory duplication.RésuméLe problème majeur dans l’implementation matérielle d’un turbo-décodeur réside dans le manque de parallélisme des algorithmes de décodage fondés sur la probabilitéa posteriori maximale (MAP). Cet article propose un nouveau procédé de turbocodage basé sur deux idées : le codage de chaque dimension par P codes convolutifs récursifs circulaires indépendants et l’imposition de contraintes sur la structure de l’entrelaceur de façon à permettre de décoder en parallèle les P codes convolutifs dans chaque dimension. La construction des codes constituants et de l’entrelaceur est décrite et analysée. Un haut degré de parallélisme est obtenu avec des performances équivalentes ou meilleures que le turbocode de la normedvb-rcs. L’architecture parallèle du décodeur permet de réduire à la fois la latence de décodage et la complexité du turbo-décodeur pour des applications à très hauts débits.

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning

We present a method to design high-throughput fully parallel low-density parity-check (LDPC) decoders. With our method, a decoders longest wires are divided into several short wires with pipeline registers. Log-likelihood ratio messages transmitted along with these pipelined paths are thus sent over multiple clock cycles, and the decoders critical path delay can be reduced while maintaining comparable bit error rate performance. The number of registers inserted into paths is estimated by using wiring information extracted from initial placement and routing information with a conventional LDPC decoder, and thus only necessary registers are inserted. Also, by inserting an even number of registers into the longer wires, two different codewords can be simultaneously decoded, which improves the throughput at a small penalty in area. We present our design flow as well as post-layout simulation results for several versions of a length-1024, (3,6)-regular LDPC code. Using our technique, we achieve a maximum uncoded throughput of 13.21 Gb/s with an energy consumption of 0.098 nJ per uncoded bit at E b/N0 = 5 dB. This represents a 28% increase in throughput, a 30% decrease in energy per bit, and a 1.6% increase in core area with respect to a conventional parallel LDPC decoder, using a 90-nm CMOS technology.

A 2.5mW inductorless wideband VGA with dual feedback DC-offset correction in 90nm CMOS technology

A low power inductorless wideband variable gain control amplifier (VGA) for baseband receivers has been designed in a standard digital 90 nm CMOS technology. The VGA was implemented using four-stage modified Cherry-Hooper amplifier with a dual feedback DC-offset canceling network, which simultaneously corrects DC offsets and extends bandwidth without a peaking inductor resulting in saving the chip space significantly. The proposed VGA has been measured using on-chip probing and achieves a 3-dB bandwidth of more than 2.2 GHz with 60 dB gain tuning range. It consumes 2.5 mW through a 1V supply (excluding the output buffer), and occupies only 0.01 mm2 active area.

A scalable LDPC decoder ASIC architecture with bit-serial message exchange

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architectures potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250Mbps, a core area of 6.96mm^2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.

Low-power static and dynamic high-voltage CMOS level-shifter circuits

Pseudo-NMOS level-shifters consume large static current making them unsuitable for portable devices implemented with HV CMOS. Dynamic level-shifters help reduce power consumption. To reduce on-current to a minimum (sub-nanoamp), modifications are proposed to existing pseudo-NMOS and dynamic level-shifter circuits. A low power three transistor static level-shifter design with a resistive load is also presented.

A degree-matched check node approximation for LDPC decoding

This paper examines ways to recoup the performance loss incurred when using the min-sum approximation instead of the exact sum-product algorithm for decoding low-density parity check codes (LDPCs). Approximations to the correction factor exactly expressing the difference between these two decoding algorithms exist for degree 3 check nodes, and can be applied to higher degree nodes by subdividing them into component degree 3 nodes. However, this results in replication of the approximation. An asymptotic expression for the correction factor at a check node of any degree is derived in this paper, and used to develop two simple approximations to the correction factor, matched to the check node degree. One has very low complexity, and both only need be applied once per check node extrinsic message. Simulation results are presented for each check node approximation when decoding a regular and an irregular LDPC. Both degree-matched check node approximations achieve sum-product decoding performance

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.

Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis

An N-symbol discrete Fourier transform (N -DFT) processor based on analog CMOS current mirrors that operate in the strong inversion region is presented. It is shown that transistor mismatch can be modeled as an input-referred noise source that can be used in system-level studies. Simulations of a radix-2, 256-symbol fast Fourier transform (FFT) show that the model produces equivalent results to those of a model that incorporates a mismatch term into each current mirror. It is shown that in general, high-radix FFT structures and specifically the full-radix DFT have reduced sensitivity to mismatch and a reduced number of current mirrors compared to radix-2 structures and have some key advantages in terms of transistor count with respect to comparable digital implementations. Simulations of an orthogonal frequency-division multiplexing system with forward error control coding, that take into account current mirror nonidealities such as mismatch, show that an analog DFT front end loses only 0.5 dB with respect to an ideal circuit.