Bruno Girodias

System level assessment of an optical NoC in an MPSoC platform

In the near future, Multi-Processor Systems-on-Chip (MPSoC) will become the main thrust driving the evolution of integrated circuits. MPSoCs introduce new challenges, mainly due to growing communication through their interconnect structure. Current electrical interconnects will face hard challenges to overcome such data flows. Integrated optical interconnect is a potential technological improvement to reduce these problems. The main contributions of this paper are i) the optical network integration in a system-level MPSoC platform and ii) the quantitative evaluation of optical interconnect for MPSoC design using a multimedia application.

MPSoC memory optimization using program transformation

Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques for parallel architectures discussed in the literature are based on a single loop nest. This article presents new techniques that consist in applying loop fusion and tiling to several loop nests and to parallelize the resulting code across different processors. These two techniques reduce the number of memory accesses. However, they increase dependencies and thereby reduce the exploitable parallelism in the code. This article tries to address this contradiction. To optimize the memory space used by temporary arrays, smaller buffers are used as a replacement. Different strategies are studied to optimize the processing time spent accessing these buffers. The experiments show that these techniques yield a significant reduction in the number of data cache misses (30%) and in processing time (50%).

Application-Level Memory Optimization for MPSoC

Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use multi-dimensional arrays to store intermediate results during multimedia processing tasks. A couple of key optimization techniques exist and have been demonstrated on SoC architecture. This paper presents these techniques and their impact on a MPSoC environment and brings forward improvements. These techniques allow for optimization of memory space, reduction of the number of cache misses and extensive improvement of processing time extensively. In this papers case study, theses techniques yield an average increase of the data cache hit rate by 20% and an average decrease of processing time by 50%

Co-simulation based platform for wireless protocols design explorations

Longer range, faster speed and stronger link are todays wireless mandatory characteristics. Tremendous efforts are being deployed to create new and improved wireless protocols. However, these new protocols are being tested in harsh and uncontrolled environments. Simulation tools help to capture the expected behavior, but the proposed designs might not work in real life situations due to lack of accurate simulation models. Testbed platforms are able to test designs in real life settings, but the flexibility of the design is reduced and design exploration becomes a complex task. This paper presents a hybrid platform composed of a simulation tool and a testbed environment, which makes it possible easily design and accurately test new wireless protocols.

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip

Multiprocessor systems-on-chips (MPSoCs) are defined as one of the main drivers of the industrial semiconductors revolution. They are good candidates for systems and applications such as multimedia. Memory is becoming a key player for significant improvements in these applications (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. The large amount of data manipulated by these applications requires high-capacity calculation and memory. This leads to the need of new optimization and mapping techniques. This paper presents a novel approach for combining memory optimization with mapping of data-driven applications. This approach consists of task graph transformation and its integration to existing mapping algorithms. Some significant improvements are obtained for memory gain, communication load and physical links.

Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications

Multiprocessor System-on-Chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. The techniques for processor design and application optimizations can be combined together for more efficient design of these systems. Thus, the memory optimization techniques improving the data locality can be combined with multithreading technology, improving the overall processor efficiency. The combination of these techniques is mainly challenged by the adaptation of memory optimization techniques to the high parallelism offered by the multithreading environments. This paper presents an in-depth analysis of the impact of multiprocessor and multithreading environments on memory optimization techniques. A discussion is provided on the different types of parallelization (fine and coarse grain) and their influence on memory optimization technique. Some improvements on existing memory optimization techniques are presented as well some adaptation necessary to use them in this type of environment.

Buffer and Register Allocation for Memory Space Optimization

In today’s embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, we propose a new technique that optimizes the use of the cache and the registers. It consists in combining buffer and register allocation to reduce the size of the temporary arrays. Firstly we use the concept of live data to replace each array by a buffer of lower size. Then we replace references to these buffers by registers. The buffer allocation step keeps only useful data in memory and the register allocation step allows taking advantage of data reuse in internal loops. Codes considered in this paper are multimedia applications structured as a sequence of loop nests. The experiments are made on Unix environment and on the StepNP simulator (MPSoC platform of STMicroelctronics). They show that our technique yields significant reduction of the number of data cache and TLB misses.

Wireless Design Platform Combining Simulation and Testbed Environments

Abstract Longer range, faster speed and stronger links are mandatory characteristics of today’s wireless systems. Tremendous efforts are being made to create new and improved wireless protocols providing these features. The complexity of these protocols requires fast and accurate validation methodologies. Simulation-based approaches for validation help to capture the expected behavior, but the proposed designs might not work in real life situations due to lack of accurate models. The approaches based on testbed platforms are able to test designs in real life settings, but the flexibility of the design is reduced and the design exploration becomes a complex task. This chapter presents a hybrid platform composed of a simulation tool and a testbed environment to facilitate the design and improve test accuracy of new wireless protocols.

Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip

Due to their great ability to parallelize at a very high integration level, Multi-Processors Systems-on-Chip (MPSoCs) are good candidates for systems and applications such as multimedia. Memory is becoming a key player for significant improvements in these applications (power, performance and area). The large amount of data manipulated by these applications requires high-capacity computing and memory. Lately, new programming models have been introduced. This leads to the need of new optimization and mapping techniques suitable for embedded systems and their programming models. This article presents novel approaches for combining memory optimization with mapping of data-driven applications while considering anti-dependence conflicts. Two different approaches are studied and integrated with existing mapping algorithms. The first approach (based on heuristic algorithms) keeps the graph transformation for memory optimization stage from the mapping stage and enables their combination in a design flow. The second approach (based on evolutionary algorithms) combines these two stages and integrates them in a unique stage. Some significant improvements are obtained for memory gain, communication load and physical links.

Architectural exploration of optical and electrical interconnects in MPSoC

MPSoC interconnect architectures require new design evolution to absorb the high data rate of the future processor evolutions and to absorb the complex data flow of the next application generations. This paper details an interconnect architectural exploration in an MPSoC environment using a multimedia application: a medical imaging. This exploration take into account two opposite interconnect technologies, optical and electrical. Depending on the application and MPSoC architecture, either electrical or optical interconnect can bring significant performance in terms of hit cache ratio and processing time.