El Mostapha Aboulhamid

Test development for communication protocols: towards automation

In this paper we give an introduction to methods and tools for testing communication protocols and distributed systems. In this context, we try to answer the following questions: Why are we testing? What are we testing? Against what are we testing?... We present the different approaches of test automation and explain the industrial point of view (automatic test execution) and the research point of view (automatic test generation). The complete automation of the testing process requires the use of formal methods for providing a model of the required system behavior. We show the importance of modelling the aspects to be tested (the right model for the right problem!) and point out the different aspects of interest (control, data, time and communication). We present the problem of testing based on models, in the form of finite state machines (FSMs), extended FSMs, timed FSMs and communicating FSMs, and give an overview of the proposed solutions and their limitations. Finally, we present our own experience in automatic test generation based on SDL specifications, and discuss some related work and existing tools.

A Survey on IP Watermarking Techniques

Intellectual property (IP) block reuse is essential for facilitating the design process of system-on-a-chip. Sharing IP designs poses significant high security risks. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we survey and classify different techniques used for watermarking IP designs. To this end, we defined several evaluation criteria, which can also be used as a benchmark for new IP watermarking developments. Furthermore, we established a comprehensive set of requirements for future IP watermarking techniques.

A SystemC/Simulink Co-Simulation Framework for Continuous/Discrete-Events Simulation

The increasing complexity of continuous/discrete systems makes their simulation and validation a demanding task for the design of heterogeneous systems. The global validation of these systems requires new techniques offering high abstraction levels and simulation accuracy from a time point of view. The main challenge is the time synchronization and the accommodation of different concepts specific to continuous and discrete models. This paper proposes a co-simulation approach that relies on Simulink for the continuous simulation and SystemC for the discrete simulation. It is based on more than one synchronization model. The synchronization and the communication are assured by co-simulation interfaces. The article also introduces the CODIS tool for the automatic generation of co-simulation instances composed of models and co-simulation interfaces. Experimental results are presented for an illustrative discrete/continuous application

IP watermarking techniques: survey and comparison

Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant high security risks. IPs can be read, copied or even partitioned to cover the authorship proof. Creators and owners of IP designs want assurance that their content will not be illegally redistributed by consumers. Consumers, on the other hand, want assurance that the content they buy is legitimate. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of IP blocks. In this paper, we outline IP watermarking and survey the current state-of- the-art of different schemes and algorithms. We also highlight the main technical problems that should be solved in order to let IP watermarking be used widely in industry.

A Public-Key Watermarking Technique for IP Designs

Sharing IP blocks in todays competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illegally redistributed by consumers, and consumers want assurances that the content they buy is legitimate. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we propose a new approach for watermarking IP designs based on the embedding of the ownership proof as part of the IP designs finite state machine (FSM). The approach utilizes coinciding as well as unused transitions in the state transition graph of the design. Our approach increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. We also define for our approach, and use experimental measures to prove its robustness.

Optimal design of synchronous circuits using software pipelining techniques

We present a method to optimize clocked circuits by relocating and changing the time of activation of registers to maximize the throughput. Our method is based on a modulo scheduling algorithm for software pipelining, instead of retiming. It optimizes the circuit without the constraint on the clock phases that retiming has, which permits to always achieve the optimal clock period. The two methods have the same overall time complexity, but we avoid the computation of all pair-shortest paths, which is a heavy burden regarding both space and time. From the optimal schedule found, registers are placed in the circuit without looking at where the original registers were. The resulting circuit is a multi-phase clocked circuit, where all the clocks have the same period and the phases are automatically determined by the algorithm. Edge-triggered flip-flops are used where the combinational delays exactly match that period, whereas level-sensitive latches are used elsewhere, improving the area occupied by the circuit. Experiments on existing and newly developed benchmarks show a substantial performance improvement compared to previously published work.

BDD minimization by scatter search

Reduced-ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, the authors study the BDD minimization problem based on scatter search optimization. Scatter search offers a reasonable compromise between quality (BDD reduction) and time. On smaller benchmarks it delivers almost optimal BDD size with less time than the exact algorithm. For larger benchmarks it delivers smaller BDD sizes than genetic algorithm or simulated annealing at the expense of longer runtime.

Automatic executable test case generation for extended finite state machine protocols

This paper presents a method for automatic executable test case and test sequence generation which combines both control and data flow testing techniques. Compared to published methods, we use an early executability verification mechanism to reduce significantly the number of discarded paths. A heuristic which uses cycle analysis is used to handle the executability problem. This heuristic can be applied even in the presence of unbounded loops in the specification. Later, the generated paths are completed by postambles and their executability is re-verified. The final executable paths are evaluated symbolically and used for conformance testing purposes.

Test cases selection from SDL specifications

Abstract Selecting appropriate test cases is a crucial activity in software testing. In this paper, we give an overview and discuss existing methods and tools for test case selection for communication protocols. More precisely, we are interested in techniques for test case generation from specification and description language (SDL) specifications and its underlying behavioral model, extended finite state machines (EFSM) and its variants.

Space: a hardware/software systemC modeling platform including an RTOS

This work attempts to enhance the support of embedded software modeling with SystemC 2.0. We propose a top-down approach that first. lets designers specify their application in SystemC at a high abstraction level through a set of connected modules, and simulate the whole system. Then, the application is partitioned in two parts: software and hardware modules. Each partition can be connected to our platform that includes a commercial RTOS executed by an ARM ISS scheduled by the SystemC simulator. One of our major contributions is that we can easily move a module from hardware to software (and vice versa) to allow architectural exploration.