Luiza Gheorghe

Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool

Continuous and discrete components may be integrated in diverse embedded systems ranging across defense, medical, communication, and automotive applications. The global validation of these systems requires new validation techniques, the main challenge being the definition of global simulation models able to accommodate the different concepts specific to continuous and discrete models. This paper presents the operational semantic for the continuous/discrete synchronization model and the formal definition of the internal architecture of simulation interfaces required for the design of a co-simulation tool for continuous/discrete systems validation

Semantics for model-based validation of continuous/discrete systems

Continuous and discrete components can be integrated in diverse systems including defense, medical, electronic, communication, and automotive applications. Given the heterogeneity of concepts that have to be taken into consideration, their design involves overcoming specific global modeling and validation challenges. This paper presents semantics for model-based validation of continuous/discrete systems. It focuses on the simulation interfaces semantics, representation and verification. The proposed approach is applied for the validation of a continuous/discrete medical system, an automatic glycemia level regulator.

Codis – A Framework for Continuous/Discrete Systems Co-Simulation

Abstract This paper presents CODIS, a co-simulation framework for continuous/discrete systems. Based on a well defined synchronization model and a generic architecture for continuous/discrete simulation models, this framework enables easy specification and automatic generation of simulation models. The supported simulators are Simulink for continuous components and SystemC for discrete components.

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip

Multiprocessor systems-on-chips (MPSoCs) are defined as one of the main drivers of the industrial semiconductors revolution. They are good candidates for systems and applications such as multimedia. Memory is becoming a key player for significant improvements in these applications (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. The large amount of data manipulated by these applications requires high-capacity calculation and memory. This leads to the need of new optimization and mapping techniques. This paper presents a novel approach for combining memory optimization with mapping of data-driven applications. This approach consists of task graph transformation and its integration to existing mapping algorithms. Some significant improvements are obtained for memory gain, communication load and physical links.

Semantics for Rollback-Based Continuous/Discrete Simulation

Modern device trends present greater challenges to design [1] because many of them integrate continuous and discrete sub-systems and therefore their design involves specific global modeling and validation approaches. This paper proposes the operational semantics for rollback-based synchronization model that may be used in continuous/discrete systems simulation. The paper also addresses the formal representation of the behavior of the continuous/discrete simulation interfaces with respect to this mode. This representation enables the definition of generic and language independent co-simulation tools that can be used to provide global simulation models for continuous/discrete heterogeneous systems. The model was validated through simulation, using UPPAAL toolbox and its formal verification was realized by defining and checking the main properties.

MP SoCs including optical interconnect: technological progresses and challenges for CAD tools design

This paper surveys the multi-technology multiprocessors systems-on-chip (MP SoC) - we emphasize the systems including optical solution for on-chip interconnects as an alternate solution for the current challenges in MP SoCs such as networks bandwidth, scalability and flexibility. We present also some tools and methodologies for global specification of multi-technology systems and the challenges for CAD tools design.

System-level design of continuous/discrete-time heterogeneous systems applied to high-speed serial link

Many existing and future systems are and will be composed by several significantly heterogeneous modules, including both continuous and discrete components. This broad class of systems includes analog/mixed-signal systems composed of RF, analog, analog-to-digital and digital-to-analog conversions, and recently, a large number of mixed-signal chips where at least part of the chip design needs to measure signals with high precision. Comparing with the digital circuits, these chips have very different design and process technology demands. This paper presents an approach for system-level design of continuous/discrete systems, focusing the role of the bottom-up iterations. The approach is applied to the design of a high-speed serial link.

Wireless Design Platform Combining Simulation and Testbed Environments

Abstract Longer range, faster speed and stronger links are mandatory characteristics of today’s wireless systems. Tremendous efforts are being made to create new and improved wireless protocols providing these features. The complexity of these protocols requires fast and accurate validation methodologies. Simulation-based approaches for validation help to capture the expected behavior, but the proposed designs might not work in real life situations due to lack of accurate models. The approaches based on testbed platforms are able to test designs in real life settings, but the flexibility of the design is reduced and the design exploration becomes a complex task. This chapter presents a hybrid platform composed of a simulation tool and a testbed environment to facilitate the design and improve test accuracy of new wireless protocols.