Bryan S. Goda

The affective dimension of pervasive themes in the information technology curriculum

The pervasive themes cited by the IT2005 Information Technology Model Curriculum are system integration, use of abstraction, user advocacy, information assurance, adaptability, professionalism and outstanding interpersonal skills. These are aspects of what we teach that pervade and tie together the IT discipline, aspects whose understanding identifies the IT professional. Pervasive themes can be characterized (Meyer,Land[14]) as transformative (change how students think), irreversible (once understood, are never forgotten), integrative (provide a framework for understanding previous concepts), boundin(serve as discipline boundaries in that understanding them identifies someone as a member of the discipline), troublesome (are difficult to teach and learn). This paper illustrates each of these characteristics using the IT pervasive themes and then proposes that an essential aspect of a pervasive theme is that it has an affective component. That is, in addition to cognitive elements (knowledge and intellectual skills), a pervasive theme includes educational objectives that treat values and attitudes. Just as cognitive objectives have a well-known hierarchy of cognitive difficulty, so also affective objectives have a (less well-known) hierarchy of increasing value commitment in which affective objectives can be placed and classified. This paper discusses the affective component in the IT2005 pervasive themes, how they are specified and classified, and how they are achieved using inculcation, role models, role playing, values clarification and analysis, and educational tasks that include natural affective consequences such as project development for real clients.

Reconfigurable FPGA's in the 1-20 GHz band with HBT BiCMOS

This paper describes the operation of a field Programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (HBT) version of the Xilinx 6200 FPGA. A new proposed device would be bitwise compatible with the 6200, but would operate in the 1-20 GHz range due to the HBT technology being used for the logic and routing and CMOS for storing the configuration bits. This is possible due to the IBM cointegration process of a HBT with a BiCMOS process. Information in this paper is based on an HBT having a f/sub T/ of 50 GHz, but later in 1999 IBM will be unveiling a process that will double the speed. By replacing and redesigning key parts of the 6200 FPGA, a 100-200X operating speedup is possible. The core logic cell in the 6200 consists of two input multiplexers and nip-flops, which can easily be converted to current mode logic (CML). Routing in a conventional FPGA is done via pass transistors, which can act like a low pass filter for a high-speed signal. A SiGe HBT CML multiplexer can be used for routing which can pass signals with a 12-14 picoseconds delay. Through the use of a side decoder, memory planes of configuration could be used to store current and future configurations. Interchange could occur between memory planes if the old flip-flop values are stored, new flip-flop values are restored, and then the new configuration plane is activated. Countless applications such as DSP, Ethernet routing, missile control, and artificial intelligence could utilize a SiGe HBT FPGA.

Faculty development in information technology education

Information Technology (IT) is an emerging discipline that is well served by faculty members with recent industry experience. Unfortunately, hiring individuals with recent experience can lead to instructors who need help integrating into an academic environment. At the United States Military Academy, our faculty recruiting model results in a turnover of approximately 20% every year. Our challenge is to provide a top notch development program in order to rapidly inculcate the new faculty with an IT appropriate pedagogical focus. This paper describes the details of our faculty development program. The formal developmental process for new instructors begins with an intensive six week summer workshop and continues throughout their time at the Military Academy. During the academic year, mentor and peer classroom visitations provide a unique opportunity for personal pedagogical growth, and periodic seminars and invited speakers help maintain technical currency. At a higher level, our Center for Teaching Excellence publishes a monthly newsletter, coordinates seminars, offers a multi-year developmental program, and presents an annual award for teaching innovation. In addition to internal programs, members of the faculty are provided support and encouragement to attend conferences and remain active in the larger IT community. The paper concludes by describing our faculty evaluation processes, which are used to assess and then improve the development program.

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGAs capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuits performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs

Field programmable gate arrays (FPGAs) are flexible programmable devices that are used in a wide variety of applications such as network routing, signal processing, pattern recognition and rapid prototyping. Unfortunately, the flexibility of the FPGA hinders its performance due to the additional logic resources required for the programmable hardware. Today?s fastest FPGAs run in the 250 MHz range. This paper proposes a new family of FPGAs utilizing a high-speed SiGe Heterojunction Bipolar Transistor (HBT) design, co-integrated with CMOS in an IBM BiCMOS process. This device is bit-wise compatible with the Xilinx 6200, with operating frequencies in the 1 to 20 GHz range. All logic and routing in this new design is multiplexer based, eliminating the need for pass transistors, the main roadblock to high speed in todays FPGAs.

Designing an interdisciplinary information technology program

We examine key factors in the design and implementation of an Information Technology (IT) major and discuss the limitations encountered in creating a new program in a resource constrained environment. The focus is on four factors. First, we discuss a learning model appropriate for IT majors who need to be prepared for graduate study in IT, the military IT environment, and the civilian IT world. Second, we examine the strengths and weaknesses of implementing the learning model by using existing courses offered by an existing organization. Third, we discuss ways to mitigate potential weaknesses of this approach. Finally, we discuss a continuous assessment and improvement process to evaluate and improve the success of the implementation.

Experiences in preparing multiple programs for a joint ABET accreditation general review

The United States Military Academy (USMA) will have seven of its programs undergo a joint review by the Engineering Accreditation Commission (EAC) and the Computing Accreditation Commission (CAC) of the Accreditation Board for Engineering and Technology (ABET). Evaluating all seven programs simultaneously allows synergy, but it necessitates coordination at the institutional level, and requires the support and cooperation of nonreviewed programs. The Department of Electrical Engineering and Computer Science will have both programs reviewed, by the EAC and CAC, respectively. There are many similarities and differences between the two, requiring internal controls, timelines, and processes to ensure correct completion of the requirements. Course directors and other faculty need guidance in preparing for the visit, managing additional administrative loads during the record year, and in understanding how assessment improves their programs. Although all of the areas mentioned above are discussed in the context of the USMA, they should prove useful to any institution preparing for an ABET visit.

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.