Kuan Zhou

3D direct vertical interconnect microprocessors test vehicle

The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated Circuits (IC) such as microprocessors have been entering the giga-hertz operating frequency range, various speed related roadblocks have become increasingly difficult to overcome. The migration to smaller devices has raised serious challenges. The major impediment to fulfill Moores Law effectively in the years to come is increasingly becoming the interconnect. ICs are using a greater fraction of their clock cycles charging interconnect wires. IC interconnect related speed degradation has stimulated much research effort in the area of low dielectric constant materials. A relatively novel approach, wafer scale 3-dimensional (3D) integration attempts to by-pass the large wire parasitics by shortening wires. This paper is going to elaborate on a 3D microprocessor test vehicle. We intend to demonstrate the speed advantages, which may be derived from 3D integration, through a combination of fabrication, testing and simulation.

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGAs capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuits performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

Gigahertz FPGAs with new power saving techniques and decoding logic

The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5 GHz have been reported However, to make the idea practical, serious power management and new architectural features have to be included, so that they can be scaled up significantly. This paper elaborates new ideas in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to cut down the number of current trees in the circuit. Selective tree shutdown has been used to reduce power consumption. A new decoding logic has been developed where the address and data lines are shared These ideas have improved the performance of SiGe FPGAs. The operating frequency of the new Configurable. Logic Block (CLB) is 6.8 GHz.

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

The 10GHz 4:1 MUX and 1:4 DEMUX implemented via the gigahertz SiGe FPGA

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

An 11 GHz FPGA with test applications

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

The gigahertz FPGA: design consideration and applications

This paper describes the implementation of a large scale SiGe FPGA that serves as a high speed FPGA test platform. In the FPGA core, 20 x 20 building blocks (Basic Cells) are used to implement logic applications. This chip contains 106 devices including SiGe NPNs and MOSFETs. This chip is fabricating with the IBM SiGe 7HP process with cut off frequency of 120GHz. The target running frequency of this FPGA is 10GHz. Clock repeaters are added for improved clock distribution. A test circuit whose building block cell runs up to 10GHz is fabricated and measured by the same process. Future work and some potential applications of the SiGe FPGA are also described.