Jong-Ru Guo

Modeling and Analysis of an 80-Gbit/s SiGe HBT Electrooptic Modulator

We present a rigorous electrical and optical analysis of a strained and graded base SiGe Heterojunction Bipolar Transistor (HBT) electrooptic (EO) modulator. In this paper, we propose a 2-D model for a graded base SiGe HBT structure that is capable of operating at a data bit rate of 80 Gbit/s or higher. In this structure, apart from a polysilicon/monosilicon emitter (Width = 0.12 μm) and a strained SiGe graded base (Depth = 40 nm) , a selectively implanted collector (SIC) (Depth = 0.6 μm) is introduced. Furthermore, the terminal characteristics of this new device modeled using MEDICI are closely compared with the SiGe HBT in the IBM production line, suggesting the possibility of fast deployment of the EO modulator using established commercial processing. At a subcollector depth of 0.4 μm and at a base-emitter swing of 0 to 1.1 V, this model predicts a rise time of 5.1 ps and a fall time of 3.6 ps. Optical simulations predict a π phase shift length (Lπ) of 240.8 μm with an extinction ratio of 7.5 dB at a wavelength of 1.55 μm. Additionally, the tradeoff between the switching speed, Lπ and propagation loss with a thinner subcollector is analyzed and reported.

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGAs capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuits performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

A high speed reconfigurable gate array for gigahertz applications

This paper describes the implementation of the next generation of a scalable SiGe FPGA in the latest IBM 8HP SiGe process (fT = 210GHz) that serves as an interleaving and de-interleaving block in a high speed reconfigurable data acquisition system. In this paper, different generations of SiGe configurable blocks (basic cells) are presented and measured. The latest generation has a 94% reduction in power consumption (from 71mW to 4.2mW) and an 83% reduction of the propagation delay (from 238ps to 42ps) compared to the first generation design. To demonstrate the SiGe FPGAs capabilities of handling GHz signals, the SiGe FPGAs are configured as a multiplexer (MUX), de-multiplexer (DEMUX) and pseudo-SERDES. For the IBM 8HP process, the MUX, DEMUX and pseudo-SERDES can achieve a transmission rate of 28Gbps. For the previous IBM 7HP case, the 4:1 multiplexer runs at a transmission rate of 8Gbps. With these design results, the SiGe FPGA is able to process GHz signals such as S and K microwave bands.

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

The 10GHz 4:1 MUX and 1:4 DEMUX implemented via the gigahertz SiGe FPGA

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBMs SiGe process, including a recent 9HP process featuring devices with a cutoff frequency (fT) of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 × 48 cell field programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (fT 1/4 825 GHz) having 100x less power consumption than conventional vertical HBTs.

Numerical investigation of a SiGe HBT electro-optic modulator

We analyzed an electro-optic modulator consisting of a heterojunction bipolar transistor (HBT) with graded SiGe composition in the base. Simulation shows single mode operation is attainable with an interaction length Lp of 40.8μm.