Bu Jianhui

A total dose radiation model for deep submicron PDSOI NMOS

In most of the total dose radiation models, the drift of the threshold voltage and the degradation of the carrier mobility were only studied when the bulk potential is zero. However, the measured data indicate that the total dose effect is closely related to the bulk potential. In order to model the influence of the bulk potential on the total dose effect, we proposed a macro model. The change of the threshold voltage, carrier mobility and leakage current with different bulk potentials were all modeled in this model, and the model is well verified by the measured data based on the 0.35 μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences, especially the part of the leakage current.

A new OLED SPICE model for pixel circuit simulation in OLED-on-silicon microdisplay design

A new equivalent circuit model of organic-light-emitting-diode (OLED) is proposed. As the single- diode model is able to approximate OLED behavior as well as the multiple-diode model, the new model will be built based on it. In order to make sure that the experimental and simulated data are in good agreement, the constant resistor is exchanged for an exponential resistor in the new model. Compared with the measured data and the results of the other two OLED SPICE models, the simulated I -V characteristics of the new model match the measured data much better. This new model can be directly incorporated into an SPICE circuit simulator and presents good accuracy over the whole operating voltage.

Transconductance bimodal effect of PDSOI submicron H-gate MOSFETs

A bimodal effect of transconductance was observed in narrow channel PDSOI sub-micron H-gate PMOSFETs, which was accompanied with the degeneration of device performance. This paper presents a study of the transconductance bimodal effect based on the manufacturing process and electrical properties of those devices. It is shown that this effect is caused by a diffusion of donor impurities from the N+ region of body contact to the P+ poly gate at the neck of the H-gate, which would change the work function differences of the polysilicon gate and substrate. This means that the threshold voltage of the device is different in the width direction, which means that there are parasitic transistors paralleled with the main transistor at the neck of the H-gate. The subsequent devices were fabricated with layout optimization, and it is demonstrated that the bimodal transconductance can be eliminated by mask modification with N+ implantation more than 0.2 μm away from a poly gate.

Analysis and optimization of tunneling-FET based on SOI

In this paper, we optimized a heterojunction SOI-TFET with high-k dielectric overlap on SiGe-source region. Mole fraction (x) of the Si(x)Ge(1−x) has an important influence in the performance of the TFET. The optimized device has achieved 50.9mV/decades SS, which breaks the 60mV/decades SS barrier. It has realized 107 Ion/Ioff ratios and the OFF-state leakage current can be lowed to 10−14 A/µm level. The ON-state drain current can reach 10−6A/µm at VDS=0.3V and the device works well at VDS=0.2V. The proposed device is optimized using 2D Synopsys TCAD simulation.

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

Deep submicron PDSOI thermal resistance extraction

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.