Du Huan

Design of a 16 gray scales 320 × 240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuits power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4 × 28.4 μm2 and the display area is 10.7 × 8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.

A thru-reflect-line calibration for measuring the characteristics of high power LDMOS transistors

The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths. An improved thru-reflect-line (TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented. According to the TRL algorithm, the individual two-port S parameters of each fixture half can be obtained. By de-embedding these S parameters of the test fixture, an accurate calibration can be made. The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width. The impedance of the transistor is obtained, and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density. From the results, it is seen that the presented TRL calibration algorithm works well.

The realization of an SVGA OLED-on-silicon microdisplay driving circuit

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm2 and the total chip occupies 15.5 × 12.3 mm2. Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

A new OLED SPICE model for pixel circuit simulation in OLED-on-silicon microdisplay design

A new equivalent circuit model of organic-light-emitting-diode (OLED) is proposed. As the single- diode model is able to approximate OLED behavior as well as the multiple-diode model, the new model will be built based on it. In order to make sure that the experimental and simulated data are in good agreement, the constant resistor is exchanged for an exponential resistor in the new model. Compared with the measured data and the results of the other two OLED SPICE models, the simulated I -V characteristics of the new model match the measured data much better. This new model can be directly incorporated into an SPICE circuit simulator and presents good accuracy over the whole operating voltage.

Effect of total ionizing dose radiation on the 0.25 μm RF PDSOI nMOSFETs with thin gate oxide

Thin gate oxide radio frequency (RF) PDSOI nMOSFETs that are suitable for integration with 0.1 μm SOI CMOS technology are fabricated, and the total ionizing dose radiation responses of the nMOSFETs having four different device structures are characterized and compared for an equivalent gamma dose up to 1 Mrad (Si), using the front and back gate threshold voltages, off-state leakage, transconductance and output characteristics to assess direct current (DC) performance. Moreover, the frequency response of these devices under total ionizing dose radiation is presented, such as small-signal current gain and maximum available/stable gain. The results indicate that all the RF PDSOI nMOSFETs show significant degradation in both DC and RF characteristics after radiation, in particular to the float body nMOS. By comparison with the gate backside body contact (GBBC) structure and the body tied to source (BTS) contact structure, the low barrier body contact (LBBC) structure is more effective and excellent in the hardness of total ionizing dose radiation although there are some sacrifices in drive current, switching speed and high frequency response.

An improved driving circuit scheme applied in extreme low-current design on OLED-on-silicon microdisplay

This paper describes an improved driving circuit scheme including a slew-rate enhancement circuit for organic light-emitting-diode-on-silicon (OLEDoS) microdisplay design. Due to the basic pixel cell area of OLEDoS microdisplay being less than 300 μm2, pixel currents are always needed to modulate from hundreds of pico-amperes (pA) to tens of nano-amperes (nA). The proposed circuit can satisfy the timing requirements (the time period of video sample signal is about 30ns) at such low current. Extra circuits introduced by the improved driving circuit scheme have a simple structure and consume little additional power in static condition.

An analytical model for the surface electrical field distribution of LDMOSFETs with shield rings

An analytical model of an LDMOSFET with a shield ring is established according to the 2D Poisson equation. Surface electrical field distribution along the drift region is obtained from this model and the influence of shield length and oxide thickness on the electrical field distribution is studied. The robustness of this model is verified using ISE TCAD simulation tools. The breakdown voltage of a specific device is also calculated and the result is in good agreement with experimental data.

Model Parameters Extraction of SOI MOSFETs

Device model parameters extraction is often performed using commercial software. But the software is usually not efficient for SOI MOSFETs because of their limitation. In this paper, the genetic algorithm is improved through combining with simulated annealing algorithm. The improved algorithm is used to extract model parameters of SOI MOSFETs, which are fabricated by standard 1.2 mum CMOS/SOI technology developed by Institute of Microelectronics of Chinese Academy of Sciences. The simulation result using this model is in excellent agreement with the experimental result. The precision is improved evidently compared with commercial software. This method requires neither deep understanding of SOI MOSFETs model nor complex computation compared with conventional methods used by commercial software. Comprehensive verification shows that this model is applicable to a very large region of device sizes

ESD protection design for the gate oxide of an RF-LDMOS

This paper presents the investigation of integrated electro-static discharge (ESD) protection design for the gate oxide of an RF-LDMOS (radio frequency lateral double diffusion MOS). Through a comprehensive discussion of experimental and simulated results, a cascoded NMOS is presented as appropriate integrated gate oxide ESD protection with a high holding voltage and a flexible ESD design window.

Holding-voltage drift of a silicon-controlled rectifier with different film thicknesses in silicon-on-insulator technology

This paper presents a new phenomenon, where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator (SOI) technology. The phenomenon was demonstrated through fabricated chips in 0.18 μm SOI technology. The drift of the holding voltage was then simulated, and its mechanism is discussed comprehensively through ISE TCAD simulations.