Bulent I. Dervisoglu

DESIGN FOR TESTABILITY USING SCANPATH TECHNIQUES FOR PATH-DELAY TEST AND MEASUREMENT

1. Abstract This paper describes a novel flip-flop design which is used in performing internal path-delay test and measurement using scanpath technique:;. Also described is the design for a boundary-scan cell that enables inpUtlOUtpUt delays to be measured. The paper includes a real-life application example.

Using scan technology for debug and diagnostics in a workstation environment

An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource which can also perform linear-feedback shift-register-based pseudorandom testing and test-result compression by signature capture. Operations of the scan subsystem are controlled from a service processor which uses a diagnostics bus to communicate with individual scan and clock resource units present on each system board. For debug purposes the service processor has been linked with a remote computer and software has been developed to display and/or modify system state variables (flip-flops). Analysis of scan overhead indicate that benefits in test and debug of the target system far outweigh the cost of implementing scan technology for the APOLLO DN 10000 workstation.<<ETX>>

Towards a standard approach for controlling board-level test functions

The architecture and some of the specific features of a scan-and-clock resource (SCR) chip are described. This chip is used in a high-end workstation product to provide access to the testability features of the individual chips and or printed circuit boards. The chip is designed to be included on each system board and is capable of controlling up to eight independent scan ports. By careful examination of different scan styles, it was discovered that there are two basic styles of scan, differentiated by their clocking mechanisms. The SCR chip uses a mode bit to specify the scan style for each port separately and by so doing to convert from the actual scan style to an internal style so that actual chip characteristics are hidden from the scan/diagnostics software. It is pointed out that using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) are emerging as a common strategy for designing testable digital systems. On the basis of experience gained from such an application, controller features which are deemed useful are discussed.<<ETX>>

Boundary-scan update-IEEE P1149.2 description and status report

The IEEE P1149.2 Working Group is developing a standard that supports boundary scan for board-level interconnect testing and supports internal scan for device- or board-level component testing. The groups overall objective is to establish minimal mandatory features that are adaptable to individual applications. P1149.2s current status and the most recent proposals being considered for the standard are described. >

Features of a scan and clock resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.

ATLAS/ELA: Scan-Based Software Tools for Reducing System Debug Time in a State-of-the-Art Workstation

Scan technology has been introduced by IBM [ 1 ] as a means of improving test coverage of digital systems. This technique uses special flip-flop designs for re-configuring all sytem variables (i.e. flip-flops) as a contiguous shift register.The APOLLO DNlOOOO is an example of a complex digital system which uses scan technology to provide improved access to the sysytem state inorder to allow improved test and prototype sysytem debug. Architectural and technological aspects of the scan sub-system of the DNlOOOO has been described elsewhere[2]. This paper describes the architecture and features of a software package which uses the DNlOO50 scan sub-system to provide an interactive debugging environment. The scan-based debugging environment so created has been a key factor in rapid debugging of the prototype DNlOOOO and has significantly contributed to the robustness of the design. An earlier paper[3] discusses the scan diagnostics for the DNl 0000.

Shared-I/O scan test

The IEEE P1149.2 standard seeks to implement several new features, such as shared-I/O cells, an optional parallel-update stage, and a high-impedance input pin. Although aspects of these features are incompatible with IEEE Std 1149.1, the working group strives to make P1149.2 consistent with the existing standards primary goals.

Microprocessor testing (panel): which technique is best?

Microprocessors, in some sense, symbolize the universe in design techniques. Virtually all general and special test techniques are applicable to some section of a microprocessor. What are some of the key companies doing for microprocessor testing today? Is there really a difference between verification and testing of a microprocessor? How much of testing can we afford to do? How do the various fault models really stack up against actual failures? What is an adequate coverage number? How effective are built-in self-test (BIST) techniques? Can we really tolerate the performance hit from BIST techniques? Is there a convergence of ideas on how to do BIST? What are the major companies doing for fault simulation, test pattern generation? Is tester performance keeping up with the advances in design? How severe is the pin count problem of the testers? What are the future challenges?