Manuel A. d'Abreu

Scheduling and hardware sharing in pipelined data paths

A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers, interconnect overhead, the size of the smallest sharable operator etc. are used to control the amount of sharing globally and produce a heuristically optimized RTL structure. The scheduling algorithm is iterated until a satisfactory structure is obtained. The algorithm also can be used for partitioning a large system into implementable pieces. The algorithm has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.<<ETX>>

The design of fault-tolerant linear digital state variable systems: theory and techniques

A theory for error detection in linear digital state variable systems is described. With the aid of a tool called the gain matrix, it is shown that the effect of error propagation along different paths of the circuit can be analyzed. For circuits with operator fanout, it is shown that despite the fact that single faulty operators cause multiple state variables to be erroneous, no more additional check variables are required than for circuits without operator fanout. It is further shown that hardware optimization can be performed by sharing hardware functions between the original state variable system and its error detection circuitry. The analysis is performed for both single and multiple faulty operators. A scheme for error correction that performs error correction in real time is proposed. Experimental results that illustrate the practical viability of the proposed scheme are discussed. >

Greedy hardware optimization for linear digital circuits using number splitting and refactorization

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications. >

Constrained conditional resource sharing in pipeline synthesis

A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing solution is a combinatorial optimization problem. The algorithm uses heuristics with a user-defined weight that trades off area versus time; the algorithm is either manually or automatically iterated by changing the weight until a solution close to the target is obtained or is determined to be impossible to obtain. The algorithm is interactive, so designers can manually determine partial or whole sharing.<<ETX>>

Flexible module generation in the FACE design environment

The Flexible Architecture Compilation Environment (FACE) provides a common object-oriented representation for design information. A module-generation system built within the FACE environment that uses parameterized procedural module descriptions is discussed. These generators capture the knowledge of a designer and facilitate a high level of reuse of the modules and leaf cells. The system provides a general mechanism to parameterize design information and supports complex generators ranging from tiled structures to entire chips. This approach is applicable to many hardware architectures. Experience in the design of working VLSI chips is discussed.<<ETX>>

Greedy Hardware Optimization For Linear Digital Systems Using Number Splitting And Repeated Factorization

Most of the current state-of-the-art behavioral synthesis tools perform a direct translation of the high-level descriptions to circuit structures in which multiplier constants are implemented as given. Some systems perform a limited amount of transformation to optimize speed and area. In this paper we propose a new optimization technique based on successive gradient method (greedy approach) to minimize the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients. Since the amount of logic required by a coefficient multiplier is dependent on the value of coefficient, the given system is transformed, using splitting of coefficients, in such a way that the new set of multiplier coefficients require less logic and area. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15% to 40% reduction in area, over conventional methods, for a set of benchmark circuits.

Concurrent error detection and fault-tolerance in linear digital state variable systems

The problem of error detection and correction (both transient and permanent) in linear digital state variable systems, a very large class of circuits used in digital signal processing and control, is considered. The case of single faulty modules (adders, multipliers, shifters, etc.) is studied, and general circuit data flow graphs (with and without fanout) that realize linear digital state variable systems are analyzed to determine how additional system states might be added to the data flow graph to achieve error detection and correction. It is seen that error detection and correction can be achieved by the addition of a relatively small amount of additional hardware which functions as the checking circuitry. Next, error detection under multiple faulty modules with and without fanout of the module outputs is studied. An analysis tool called the gain matrix is introduced. The problem of fault location and correction of single faults is discussed. Recursive as well as nonrecursive systems can be handled.<<ETX>>

Automatic test generation for linear digital systems with bi-level search using matrix transform methods

A hierarchial testing approach for linear state variable digital systems based on matrix manipulation and constrained low-level test generation is reported. FEAST (functional extractor and sequential test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. CREST (constrained sequential test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. The approach was found to perform better than automatic test generation at the gate level using existing algorithms for several large circuits.<<ETX>>

Syndrome-based functional delay fault location in linear digital data-flow graphs

A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components.<<ETX>>

Delay fault testing of iterative arithmetic arrays

Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.<<ETX>>