Bup-Joong Kim

The design of congestion manageable multiprocessor interconnects in a high capacity router

This paper is about multiprocessor interconnects for a high capacity router. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when inter-processor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for inter-processor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests three ways to build multiprocessor interconnects and discusses them in the view of congestion handling ability and implementation feasibility.

Merging existing network nodes into a new combined node

In order to improve network services and lower the cost of them, there are attempts to enable communication nodes to perform various roles. To add more functionality and roles to communication nodes, existing communication nodes should be replaced with new ones, which lead to burdensome initial cost to service providers. Therefore, it is required a method of enabling existing communication nodes to perform a new function as well as exiting functions without introducing new communication nodes. In this paper, we propose a method for integrating the existing multiple communicating nodes into one combined node. It is shown that multiple networking nodes operate as a combined node by connecting them physically and logically, assigning specialized roles to them, and making them share common control data. With intent to explain the advantages of the combined node, we estimate and compare the resource requirements for a combined node and its corresponding separate nodes. Taken as a whole, a considerable amount of node resources can be saved in the combined node due to resource sharing among the component nodes. The resulting surplus resources after merging existing network nodes into a new combined node can be used as a basis for the expansion of existing services and the introduction of new network services.

Redundant multiprocessor interconnects for the high capacitor router built on ATCA

This paper is about multiprocessor interconnects for the high capacity router built on ATCA (advanced telecom computing architecture) platform. Multiprocessor inter-connection in ATCA brings some design issues when it comes to satisfy the constraint and specification of ATCA platform. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when inter-processor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for inter-processor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests several methods to build multiprocessor interconnects in ATCA and discusses them in the view of redundancy, congestion handling ability, and implementation feasibility

Design and implementation of redundant multiprocessor interconnects in a high capacity router

This paper is about multiprocessor interconnects for the high capacity router built on ATCA (advanced telecom computing architecture) platform. Multiprocessor interconnection in ATCA brings some design issues when it comes to satisfying the constraint and specification of the ATCA platform. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when interprocessor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for interprocessor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests several methods to build multiprocessor interconnects in ATCA and discusses them in the view of redundancy, congestion handling ability, and implementation feasibility

Processor time synchronization in packet-optic data transport system

The following description relates to a processor time synchronization apparatus and method in a packet-optic data transport system which includes a plurality of processors and line interfaces, the apparatus and method capable of performing reliable systems external and internal high time-resolution time synchronization, and sharing time information by use of a simple structure at a low cost.

Network storaging service for fragile node data

The main functions of a networking device are to relay packets to their destinations, exchange and share route information between networking devices, prevent attacks of illegal or malicious packets, authenticate users and grant the right to use network resources, and so on. Thus far, a networking device has generally been thought of as a point through which data passes rather than stays at. In a dangerous environment, a node group constituting a small scale wireless network or a node operating by itself may transfer data that is almost impossible to retransfer to a server. In this case, it is possible to easily establish a reliable network and efficiently use network resources when a networking device positioned at the entrance of the Internet or the proprietary networks has a function of storing and transferring the data. The present paper discusses network storaging service and its related devices having a black box function capable of supporting transfer of an aperiodic or final message of a specific node or node group that might be lost due to an unstable network to a final server or host without any accident. The above-described networking device selects node data required to be stored in a black box, stores it in a networking device functioning black box, and transfers it in response to a request from an external device such as a host, thereby transferring an aperiodic or final message of a specific node or node group that might be lost due to an unstable network to a final server or host.

Demonstration of packet-optic integrated transport system

We propose and experimentally demonstrate a packet optical integrated transport system. The proposed system supports packet transport layer features based on PBB-TE. The restoration time from a link failure is measured to be about 20 ms and 11.8 ms, respectively, in the packet transport layer and optical transport layer. The measured restoration time is much smaller than the 50 ms industry requirement for real-time services. The fast restoration time allows the proposed packet-optic integrated transport system to offer high availability and reliability which is a requirement for transport networks.

High available system control network in the packet transport system

This paper is about design and buildup of multiprocessor interconnects in the packet transport system. To keep pace with expansion and growth of internet and data communication, constant enhancement and upgrade of packet transport system is required. As network adopts new services like IPTV, VoIP, and VLAN, processing power of packet transport system should be easily and dynamically added to the system for supporting highly compute-power requiring jobs. The processing power of system depends on the number of processors, the clock speed of each processor, efficiency of operation system in data centric processing, proper distribution of system works, and robust and high bandwidth interconnects (system control network) among processors. This paper suggested several methods for the system control networking in the packet transport system and reviewed each method in the view of internal and external expansion of system control network, loop elimination, and redundancy support.

The design of multiprocessor interconnects in a high capacity router

This paper is about multiprocessor interconnects for a high capacity router. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when interprocessor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for interprocessor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests three ways to build multiprocessor interconnects and discusses them in the view of congestion handling ability and implementation feasibility