Burhanuddin Yeop Majlis

Design and Fabrication of MEMS Micropumps using Double Sided Etching

In this paper, we report a simple technique for the fabrication of planar valveless micropumps. The technique utilizes MEMS fabrication methods by using a double sided etch technique. Instead of using several masks and process steps, an anisotropic wet etch technique at both sides of a silicon substrate is implemented at the same time for creating the pump membrane and the diffuser/nozzle elements. A planar diffuser and a nozzle element of the pump, as well as a 150 μm thick silicon membrane, are designed and fabricated using only three pattern process steps. An actuator-chamber and a pump-chamber with depths of 250 μm are formed after 250 min KOH etching, while the diffuser/nozzle element with a depth of 50 μm are sequentially formed after chamber forming. The process is simple and reproducible which opens the opportunity for fast prototyping of MEMS micropumps.

Comparative study of stack interwinding micro-transformers on silicon monolithic

Interwinding planar micro-transformers are developed using micro-machining technique. The transformers with a vertically stack coil structure on silicon monolithic substrate are designed to achieve high coupling and high inductance value in a relatively small coil area. In this work, various types of stack interwinding transformer are fabricated, measured and compared. The results show that the metal-to-metal effect of a multi-layer structure contributes to the significant increase of parasitic capacitances and hence limits the operating frequency. Moreover, the lumped element parameters are analyzed by extracting the measured S-parameter. This investigation can give important information for the future development of three-dimensional RF devices.

Deflection analysis of epitaxially deposited polysilicon encapsulation for MEMS devices

Numerical and simulation studies are done to determine deflection behavior of epitaxially deposited polysilicon encapsulation. Polysilicon encapsulation, which is used as physical protection for moving parts of MEMS devices, is applied with external pressure to replicate packaging processes. Polysilicon encapsulations thickness 10, 20, 30, and 40 micron with seal oxide of thickness 2, 4, 6, 8, and 10 micron are analyzed. Ritzs and energy methods are used to numerically approximate surface deflection of polysilicon encapsulation when perpendicularly loaded with a uniform pressure varying from 10 to 100 atm. Simulation was done using CoventorWare ver.2001.3 software. It is observed that numerical analysis values approximate theoretical values for small deflection (W >t). Thus, numerical analysis could be use to predict deflection behavior of encapsulation in that region.

Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG) as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP) as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

Formation of thick spin-on glass (SOG) sacrificial layer for capacitive accelerometer encapsulation

This paper presents a method to form thick spin-on glass (SOG) sacrificial layer for accelerometer encapsulation fabrication. SOG is chosen as the sacrificial material because it is easy to apply, has good thickness uniformity, and can be easily etched back before densification. Siloxane type SOG is applied on blank wafers and accelerometer patterns by multiple spin, bake, and cure processes. A series of gradual hot plate baking up to 250°C are experimented for each spun layer. After multiple spin and bake, the SOG layers are etched back in hydrofluoric acid (HF) solution of various concentrations to form rectangular encapsulation bases. 25 samples are prepared for SOG thickness uniformity characterization. Center thickness and four perimeter thickness measurements are taken for each sample using thin-film mapper. These five measurements are averaged to get sample thickness. Two surface profiler measurements are taken for each sample perpendicularly to each other using Tencor surface profiler. The minimum reading is subtracted from the maximum reading to get sample variation. Upon SEM inspection, mildly sloped etched walls from HF etching are observed. No surface cracking was visible. Shallow trench patterns are apparent on SOG deposited on accelerometer pattern. The average sample thickness is 5 μm with 3.7% thickness variation across samples. The average variation within each sample is 0.14 μm with an average of 2.6% thickness variation within sample. These thickness variations are acceptable for encapsulation structure deposition.

Simulation for deposition of ZnO thin film layer by kinetic Monte Carlo method

Abstract Kinetic Monte Carlo method was used to simulate the deposition of ZnO thin film layers. For this simulation, parameters for atom absorption, desorption and surface diffusion were incorporated to perform more realistic model of deposition. A new approach was used where the diffusion process was integrated as part of the deposition process. Simulations were carried out at different substrate temperatures. Two- and three-dimensional growth mechanisms were simulated using this model. Surface roughness can be estimated from the ratio of the atoms at the edge of the islands to the total surface sites. The number of Zn and O adatoms on the surface as a time function was analysed.

Fabrication of Platinum Membrane on Silicon for MEMS Microphone

Platinum membrane with silicon nitride layer is fabricated and analyzed. The membrane, which is designed for MEMS microphone application, is fabricated using sputter platinum and CVD silicon nitride. Membranes with sandwich layer of platinum-nitride-platinum with thickness of 6.35 mum are successfully fabricated. Deflection of the fabricated membrane corresponding to given pressure is measured using Tencor surface profiler. It is observed that deflection at its center is proportional to applied pressure for pressure between 20 Pa to 200 Pa. Average center deflection for applied pressure of 200 Pa is measured to be 0.41 mum. The fabricated platinum membrane is deemed suitable for MEMS microphone application due to its linear deflection response in acoustic pressure range.

High-frequency analysis on surface micromachined on-chip transformers with stacked interwinding coil structures

On-chip micro-transformers with a stacked interwinding coil have been developed. The transformer is fabricated using simple and cost-effective MEMS surface micromachining. High-frequency characteristics of the transformer are analyzed by comparing its performances for various coil structures and substrate materials, respectively. The results show that the RF performance of the glass-based transformer is improved compared to that of a silicon-based transformer. An analysis of various coil configuration leads to the conclusion that the metal-to-metal capacitance has a significant influence on the RF characteristics. The process fabrication of the device is simple, highlighting good prospects for future three-dimensional RF-MEMS device application.