Günter Märzinger

A quad-band low power single chip direct conversion CMOS transceiver with /spl Sigma//spl Delta/-modulation loop for GSM

This paper presents a fully integrated quad band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 120 nm CMOS technology. The fully integrated VCO operates at 4 GHz with a frequency range that can be programmed by 10 bit. The output power of the transmitter is 8 dBm and no TX SAW filter is needed due to the low phase noise of -162 dBc/Hz at 20 MHz offset frequency. The inband phase noise of the synthesizer is only -100 dBc/Hz and an overall phase noise error of 1.6/spl deg/ rms has been measured. The receiver has constant gain of 57 dB and fits to a baseband processor providing a 14 bit ADC. The noise figure in all bands is below 3 dB typically. The chip is housed in a 48 pin VQFN package.

A robust GSM/EDGE transmitter using polar modulation techniques

A key property of polar modulator systems is the matching between amplitude and phase path. This paper shows how mismatches between these paths degrade performance and introduce difficulties in designing GSM/EDGE systems. A transmitter overcoming these problems is presented. The chip has been implemented in a 0.13mum CMOS technology, with a nominal margin of 7 dB to the critical 400 kHz specification and a transmit EVM of 2.5%

Fractional-N Phase Locked Loops and It’s Application in the GSM System

This paper presents an overview of the fractional-N frequency synthesis technique. After a short excursion into the history of δσ modulation, different fractional-N techniques are shown. Following this, the δσ fractional-N PLL is explored in detail, and important results relating to fractional-N PLLs are presented. In the next section the blocks of the analogue part of the PLL are listed, and relevant design criterions are discussed. Finally the specifications imposed by the GSM system are mentioned, and two techniques for using a fractional-N PLL as a GMSK modulator are shown.