Christian Münker

A quad-band low power single chip direct conversion CMOS transceiver with /spl Sigma//spl Delta/-modulation loop for GSM

This paper presents a fully integrated quad band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 120 nm CMOS technology. The fully integrated VCO operates at 4 GHz with a frequency range that can be programmed by 10 bit. The output power of the transmitter is 8 dBm and no TX SAW filter is needed due to the low phase noise of -162 dBc/Hz at 20 MHz offset frequency. The inband phase noise of the synthesizer is only -100 dBc/Hz and an overall phase noise error of 1.6/spl deg/ rms has been measured. The receiver has constant gain of 57 dB and fits to a baseband processor providing a 14 bit ADC. The noise figure in all bands is below 3 dB typically. The chip is housed in a 48 pin VQFN package.

A robust GSM/EDGE transmitter using polar modulation techniques

A key property of polar modulator systems is the matching between amplitude and phase path. This paper shows how mismatches between these paths degrade performance and introduce difficulties in designing GSM/EDGE systems. A transmitter overcoming these problems is presented. The chip has been implemented in a 0.13mum CMOS technology, with a nominal margin of 7 dB to the critical 400 kHz specification and a transmit EVM of 2.5%

Digital RF CMOS transceivers for GPRS and EDGE

A GPRS RF solution using sigma-delta modulation and an EDGE RF solution using digital polar modulation are presented. The single-chip, quad-band transceivers have been implemented in a 0.13 /spl mu/m CMOS technology. The lock-in time of the sigma-delta modulator with integrated loop filter is less than 120 /spl mu/s with a phase error of 1.2/spl deg/ RMS and an output power of 3.5 dBm; it is fully compliant to the GSM specification. The EDGE transceiver shows a nominal margin of 11 dB to the critical 400 kHz specification with a transmit EVM of 2.5%.

Spectral PLL built-in self-test for integrated cellular transceivers

A built-in self test (BIST) solution for the on-chip spectral verification of a 4 GHz phase-locked loop (PLL) is presented. The PLL is embedded in an integrated cellular RF transceiver in a 130 nm CMOS technology. The BIST blocks enable the detection of catastrophic and many parametric faults by measuring the PLL frequency response and checking for spurious sidebands and excessive in-band phase noise without external test equipment. Multi-tone stimuli with a spurious-free dynamic range (SFDR) of 60 dB are generated on-chip, the PLL RF response is demodulated and digitized in an on-chip digital FM discriminator. Spectral analysis is performed using digital narrowband filtering, achieving an SFDR of 45 dB. The fully digital BIST blocks require a chip area of only 0.06 mm2 and do not compromise the performance of the PLL itself.

Panel Discussion: Life Begins at 65 - Unless You Are Mixed Signal?

The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table will analog designers of Bob Peases generation sit: the IP provider or the chip company? Or are their skills redundant for the 65 nm analog design challenges?