Byeong Min

Beyond UVM for practical SoC verification

As the size and complexity of SoC design grow, an efficient and structured verification environment is becoming more important than ever before. It is because many engineers with different knowledge and skills are involved in SoC verification, and they have to deal with different aspects of verification. This paper looks over the diversity of SoC verification and suggests a practical application method of UVM (Universal Verification Methodology) to build an efficient and structured verification environment which meets various requirements of SoC verification. This paper shows standardized and well-organized testbench architecture that includes directory structure of testbench files, and mechanism such as interface and handles across the components. The proposed UVM application method helps testbench developers maintain consistency of testbenches and reduce the quality gap among verification works that are done by multiple verification engineers, by using standardized testbench. It ensures that IP verification engineers do their job independently and the testbenches can be reused in top level verification environment. In addition, it provides a good infrastructure to hardware designers, who have little knowledge about verification languages and methodologies, and who want to write directed test cases only. The proposed method has been validated with a set of reference testbenches developed for an application processor SoC.

A practical approach of memory access parallelization to exploit multiple off-chip DDR memories

3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).

Reusable platform design methodology for SoC integration and verification

Today system-on-a-chip (SoC) is like a black hole which draws all the important IP/cores in a digital system. Current SoC design methodologies are no longer adequate to meet the challenges of SoC design productivity, design quality and diminishing time-to-market window. This paper describes an innovative SoC platform integration and verification design methodology to enhance design productivity based on IP reuse and IP-XACT standard. Platform integrator including RPTKit (reusable platform toolkit) is developed to improve the efficiency and reliability in platform integration, and platform verifier to improve verification setup time and work efficiency. Several cases of SoC platform designs substantiate the validity and capability of the platform integrator and verifier, which reduced the total SoC integration and verification time by more than 30%.

Design Automation of Pixel control block for productivity enhancement

To enhance design productivity, we propose a design methodology for automatic RTL generation of timing control block from user defined specification. We also provide error detector to reduce human error on specification to shorten design time. Experimental result shows that we can reduce overall design time by 70% while keeping area overhead lower than 5%, compared to that of manually optimized design.

An open-loop flow control scheme based on the accurate global information of on-chip communication

3D stacked memory is being adopted as a promising solution to offer high bandwidth and low latency in memory access. Compared with the on-chip network design with conventional off chip memory, it gives a new problem of minimizing communication conflicts since multiple concurrent high bandwidth data transfers will flow through the on-chip network. In order to tackle this problem, we propose applying an open-loop flow control scheme based on the accurate global information (destination and status) of on-chip communication. The proposed open-loop flow control scheme exploits the information and selectively buffers and arbitrates data transfers to remove conflicts at destinations in a preventive manner. As an implementation of the presented scheme, we present on-chip buffers called Buf3Ds that share the global information with each other to perform the selective buffering and arbitration of data transfers. Experiments with synthetic test cases and an industrial strength DTV design show that the proposed method improves aggregate memory bandwidth significantly (average 19.0 %~25.8 % in the synthetic cases and up to 18.4 % in the DTV case) with a small area overhead (15.2 % in the DTV case) of on-chip network.

How to automate millions lines of top-level UVM testbench and handle huge register classes

Not only design automation, but also testbench (TB) automation heavily affects design period, so that diverse TB automation solutions have been developed and applied to the verifications ranging from IP level to top-level. Top-level verification environment is much more complex and big, approximately 2M lines of code (LOC), so automatic generation of top-level TB is an inevitable process for competitive design period. This paper presents an experience of SV (SystemVerilog) UVM (Universal Verification Methodology) TB automation on an over 100M gate top level SoC design. Most of the TB, 88% of 2M LOC except test scenarios and user codes, has been automatically generated by the proposed automation solution. The automation solution has strong flexibility and high level maintainability upon frequent specification changes. Also, the configurable TB for various DUTs resulted 50% simulation performance enhancement.

Scalable parallel event-driven HDL simulation for multi-cores

Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms with some success. However, event-driven simulation of designs modeled in HDL (Hardware Description Language) has not achieved meaningful progress so far. This paper proposes a highly scalable parallel, event-driven HDL simulation method, based upon accurate stimulus prediction. The paper presents the basic idea of this approach and discusses why this new method is ideally positioned for achieving high parallelism with NUMA architecture.

System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system

Virtual platform is renowned for architecture exploration and validation, early software development, hardware/software co-development of Electronic System Level (ESL) System-on-Chip (SoC) design process. In Virtual Platform System (VPS), multi-level abstraction models should be properly adopted to achieve higher simulation performance while maintaining the platform design efforts as minimal as possible. For architecture validation, cycle-accurate system-level IP models are required to produce accurate performance simulation results. However, cycle-accurate model description often results in long modeling time and cycle inaccuracy due to complex timing behavior of given IPs. Therefore, RTL co-simulation has been widely used to avoid cycle-accurate model creation in system-level design process. In this paper, we suggest the Hybrid Virtual Platform System (H-VPS) to accelerate simulation speed by adopting co-emulation scheme into VPS while keeping cycle accuracy and minimizing risk of model creation. The experimental results of co-emulation show 12-48Kcps simulation speed, which is 6-62 times faster than VPS simulation time and is enough for architecture exploration and validation.

Millions to thousands issues through knowledge based SoC CDC verification

As power consumption becomes one of the most important characteristics, the number of clocks increases to implement low power features efficiently in modern mobile AP designs. In this circumstance, asynchronous design and “Clock Domain Crossing (CDC)” verification are becoming one of the biggest challenges on over 100M gate SOC designs. Tricky setup due to complex clock relations and complex design, long run time, huge number of false-errors and various operation modes are the known problems of top-level CDC verification. Among the difficulties, 70,000 ~ 100,000 issues after CDC analysis in an over 100M gate SOC overwhelm designers with its huge volume. This paper presents a comprehensive study on “huge number of false-errors after CDC analysis,” and shows the categories of all types of false-errors and causes, like wrong setups, unidentified static signals, broken asynchronous interfaces etc., which are contributing to a huge number of false-errors. Also, knowledge based solutions for known culprits are presented. It is shown that 95% of false-errors could be eliminated efficiently with the proposed knowledge-based solutions through our 3 case-studies.

Verification of massive advanced node SoCs

As the complexity of SoC design grows more than 2X a year, the time spent in logic simulation is exponentially growing. It is getting hard to meet the project schedule with existing simulation techniques. This paper proposes a new technique called Incremental Elaboration. The increased design complexity significantly impacts on elaboration time among the simulation process because hundreds of millions modules are elaborated and connected in the elaboration step. The elaboration time often takes more than 5 hours in full timing simulation. Long elaboration time degrades efficiency of verification because verification activity requires a lot of iterations. The elaboration time can be reduced by 80~90% using the proposed Incremental Elaboration technique. Application to the regression environment showed total regression time can be reduced by 42% and disk spaces for regression runs can be reduced by 96%.